You can find some answers to your technical questions below. Simply select the category for which you need to find an answer, and then select the title of the subject you are interested in to see the detailed question and answer.
(Click to expand or close subjects)
Manually install the usb driver on your host PC to communicate with your PicoSDR. http://www.ftdichip.com/Drivers/VCP.htm (Other OS) (Windows 7) http://www.ftdichip.com/Drivers/CDM/CDM20830_Setup.exe (Windows 7)
Solution: There is a difference between rev D and rev E board that may cause example to crash. Everything is further explained on the support Xilinx site. http://www.xilinx.com/support/answers/44814.htm
The ADACMaster III module can be controlled with the functions of the board software development kit (BSDK) and the model-based development kit (MBDK) associated to your product. A specific license for these packages must be purchased.
The following table shows the default design resource allocation.
| Resource | Used | Accessible | % of use |
| Slices | ± 2,02 | 15.360 | 13 |
| DCM | 3 | 8 | 37 |
| BUFG | 9 | 32 | 28 |
| RAMB16 | 2 | 192 | 1 |
| DSP48 | 1 | 192 | 1 |
No, it is not necessary.
The MULTI integrated development environment and tools suite from Green Hills Software can be used to target the ARM portion of the DM6446 running the INTEGRITY RTOS.
Yes, a community (ossie.wireless.vt.edu/trac/wiki/SffsdrLinux) offers open source SFF SDR development platform drivers for Linux and the Open Source SCA Implementation ::Embedded (OSSIE).
Important: Read carefully before proceeding and proceed at your own risk. Nutaq offers no support for these software products because they are not supplied by Nutaq.
Yes, an INTEGRITY kernel BSP is supplied with the software accompanying your product.
The DM6446 JTAG interface on the SFF SDR development platform or evaluation module is a 1.8-V, 14-pin connector. Nutaq recommends using one of the following JTAG emulators to interface with the DSP core of the DM6446:
+ Spectrum Digital XDS510 USB JTAG emulator. This emulator is 3.3-V and 5-V compatible. It requires using a voltage shifter to be 1.8-V compatible.
+ Spectrum Digital XDS510 USB PLUS JTAG emulator with 14-pin target adapter cable.
+ Spectrum Digital XDS510PP PLUS JTAG scan path emulator pod.
+ Spectrum Digital XDS560R USB JTAG emulator with 14-pin JTAG header.
Other JTAG emulators compatible with the DM6446 DM SoC core should also function adequately.
Yes, Nutaq offers boards that interface with the digital processing module.
The ADACMaster III module interfaces through the expansion connector.
The RF modules interface through the GPIO connector and can also be connected to the ADACMaster III through the SMA connectors. The supported RF modules are:
+ The Low-Band Tunable RF Module
+ The High-Band Tunable RF Module
+ The 2.5 GHz WIMAX Wideband RF Module
+ The 2.5 GHz WIMAX Narrowband RF Module
No other expansion boards are developed by Nutaq at this time. It is however possible for you to design your own expansion board and connect it through the expansion connector or the GPIO.
Possible transfer rates depend on the type of development that you are performing and also on the type of design that you are implementing (in terms of bandwidth, throughput, and data formatting). Benchmarks show possible transfer rates reaching 20 MBps with language-based development.
Note: Refer to the SFF SDR User’s guide for details on how to achieve this transfer rate.
The DSP portion of the DM6446, the Virtex-4 SX35 FPGA of the digital processing module, and the Virtex-4 FPGA of the ADACMaster III can all be targeted through this development method.
No, the DDR2 SDRAM cannot be upgraded beyond 128 MB.
No, the SD memory card is not supported.
The ADACMaster IIIof a SFF SDR development platform has two RX channels (ADCs) and two TX channels (DACs). Therefore, the number of RF modules that can simultaneously be interfaced to a SFF SDR depends on the number of RX/TX channels your RF module needs.
Examples:
A. Low-band and High-band RF modules use 1 ADC channel and 2 DAC channels; therefore, only 1 module can be used at a time.
B. WiMAX RF modules use 1 ADC channel and 1 DAC channel; therefore, 2 RF modules can be used simultaneously.
The following list of components and interfaces can be controlled with both the BSDK and MBDK design flows:
+ Audio codec
+ LED
+ Push buttons
+ DIP switches
+ DSP-FPGA data bus
The ARM runs the INTEGRITY RTOS which includes:
+ Start-up sequence and initialization
+ Ethernet management
+ Central communications engine (CCE)
+ ARM/MSP430 communications (manages power monitoring)
+ File system management
The targetable processors are:
+ The ARM and DSP portion of the DM6446 chip.
+ The Virtex-4 SX35 FPGA of the digital processing module.
+ The Virtex-4 FPGA of the data conversion module.
When the required clocks are all set to 30.72 MHz, the PLL is bypassed and therefore does not lock since it is not used.
The digital processing module is not offered with FPGA models other than the Virtex-4 SX35 in the case of single-unit orders. In the case of bulk orders; however, Nutaq can accommodate. Contact Nutaq for details.
The ADACMaster III is now only offered with Virtex-4 SX35 FPGA.
The C64+ DSP core can process 4,752 8-bit MMAC or 2,376 16-bit MMAC at 594 MHz. The SX35 Virtex-4 FPGA has 15,360 CLB slices, 192 18-kilobit blocks of RAM, and 192 XtremeDSP slices.
In a Radio420x FPGA design, the design clock is typically the clock received from the Radio420 on FMCCLK0. This clock is set to the same frequency as the Radio420's ADCs and DACs. To run the design at a specific frequency, the Radio420's ADC and DAC clock must be initialized to that frequency.
For example, in the Radio420 Record/Playback example, the ADC/DAC frequency is set (to 40.96MHz) using this define:
#define ACQUISTION_FREQ FMCRADIO_DATARATE_REF_30_72MHZ_40DOT96MHZ
To change the design clock frequency, simply replace FMCRADIO_DATARATE_REF_30_72MHZ_40DOT96MHZ with the frequency value in samples per second.
ex.: #define ACQUISTION_FREQ 10000000
Note: The ADC and DAC frequency is set at the number of I samples + Q samples per seconds sent or received. Therefore, if the design expects 10 million I samples and 10 million Q samples per second, the frequency should be set to 20000000.
During the RX DC offset calibration, the FPGA averages the signal received to calibrate the DC offset. Typically, when an error occurs, it is because the acquired signal saturates at the ADC and is clipped when sampled in the FPGA. Reduce the power inputted to the Radio 420 RX or reduce the RX gain to avoid signal saturati
ADP software versions 5.5.0 and prior do not correctly support the Radio420x revisions C and D. You should update your ADP software to version 5.6.0 or later to use them. The revision B board is correctly supported by versions 5.5.0 and prior.
When starting a Debug session in XSDK, the program cannot be loaded into the memory and the following error message is displayed:
How can this problem be solved?
Answer:
When this happens, disconnect the JTAG USB cable, close SDK, and turn off the ML605.
Make sure all SDK processes are stopped after closing the SDK window. Sometimes, javaw.exe software is still running and must be close manually in the Windows Task Manager dialog box.
Make sure the DDR3 SODIMM memory is correctly connected to the ML605. To do so, remove the DDR3 SODIMM memory and insert it back.
Turn on the ML605, connect the JTAG USB cable, and reopen SDK.
Program the FPGA with the generated bitstream.
Starting a Debug session should now work.
On an MI125-32 stack, the external clock and trigger must be connected to the card sitting directly on the carrier (MI125-16E). This card is the clock master for the stack.
The maximum throughputs obtained are:
From the embedded processor blade to the FPGA: 543 MBytes/second
From the FPGA to the embedded processor blade: 265 MBytes/second
These benchmarked values were obtained using a Perseus revision C and an SAMC-514 processor (Fedora 17) in a VT852 Vadatech chassis, running the PCI Express RTDEx example from the ADP release 6.1.
To read/write from/to the ADC, put the following pins to the specified levels:
+ ADC SPI Enable = E3 Low (access enabled)
+ DAC SPI Enable = E2 High (access disabled)
+ PLL SPI Enable = F5 High (access disabled)
To read/write from/to the DAC or PLL, put the ADC SPI Enable to High and the corresponding Enable pin to Low. Make sure there is only one pin Low and the other two High.
The F4 SPI_SDO pin is linked to all SPI chips of the ADAC250 and routing of the SDO signal is switched by the chip select pins. Make sure all chip select are high except the ADC chip select (E3 pin) and try to read a known value. You can also try to write then read back a value.
The following pins are not used in the software packages:
| Pin | Pin number | Direction | Type |
| AVR_RXD | AW35 | IN | LVCMOS25 |
| AVR_TXD | AY34 | OUT | LVCMOS25 |
| E_KEY0_FPGA | D15 | INOUT | LVCMOS25 |
| E_KEY1_FPGA | C15 | INOUT | LVCMOS25 |
| E_KEY2_FPGA | G12 | INOUT | LVCMOS25 |
| E_KEY3_FPGA | H13 | INOUT | LVCMOS25 |
| CUSTOM0_FPGA_IO | F15 | OUT | LVCMOS25 |
| CUSTOM1_FPGA_IO | AW16 | OUT | LVCMOS25 |
AVR_RXD and AVR_TXD are UART links RX and TX between the FPGA and the AVR.
The other pins are either GPIO pins or a SPI link between the FPGA and the AVR. There is also no code on the AVR that uses these pins.
I tried to program the bitstream application into the flash of the Perseus. However, the system does not boot anymore and shows following the error message.
Answer:
The Uboot and Linux kernel has been corrupted or erased. Please proceed as follows.
+ Get a copy of the u-boot.elf file and put it in the ‘c:’ folder.
+ Connect the JTAG programmer to the Perseus.
+ Connect to the Perseus serial port using Putty.
+ Open Xilinx Platform Studio.
+ In the menu go to Debug> Launch XMD.
+ When XMD is open enter the following commands:
"connect mb mdm"
"dow c:/u-boot.elf"
"run"
The Perseus should reboot and start properly. Perform the "Programming the Linux firmware in the flash memory" procedure (in Perseus User’s guide refer to the section on programming the Linux firmware in the flash memory) with the ‘u-boot-s.bin’ and ‘u-boot.elf’ files located in your ‘ADPROOTfpgabin’ folder.
Do not forget to replace ‘ADPROOT’ by the path where you installed the ADP software.
WARNING: EDK:1687 – Invalid path specified for ModuleSearchPath in XMP file. Please make sure that the directory specified exists.
ERROR: EDK: 4110 – IPNAME: lyt_axi_emac_rtdex, INSTANCE: axi_emac_rtdex – cannot find MPD for the pcore “lyt_axi_emac_rtdex_v1_00_a” in any of the repositories –
C:testexamples_perseus6010perseus6010_radio420x_rtdex_record_playbackedkperseus6010_radio420x_record_playback.mhs line 493.
WARNING: EDK:4264 – elf file specified with tag ElfImp: C:testfpgabinperseus601x_default_linux.elf not found INFO:EDK – Resetting ElfImp tag in the project file…
WARNING: EDK:3362 – Cannot open project due to errors.
Answer:
The XPS projects use relative paths to find the required files. If the project file was moved to a different folder, in or out of the ADP installation hierarchy, the project will not find the files and will not be able to open them.
It is recommended to use Windows 7 (64-bits) and have at least 10 GB of RAM.
Yes, please consult the software development tools section on our Web site.
The JTAG driver is being held by another instance of a Xilinx program. When it happens, disconnect the JTAG USB cable, close SDK, and turn off the Perseus.
Make sure all SDK processes are stopped after closing the SDK window. Sometimes, javaw.exe software is still running and must be close manually in the Windows Task Manager dialog box.
Turn on the Perseus, connect the JTAG USB cable, and reopen SDK. FPGA programming should now work.
In Visual Studio, when building an example in a 64-bit configuration, the project build is skipped and nothing happens.
Answer:
To compile a 64-bit project with Visual Studio, you must select the X64 Compilers and Tools check box during the Visual Studio installation.
Nutaq does not support the build of custom C programs for the MicroBlaze in MBDK generated bitstreams. However, the following can help you setup your XSDK project.
– The MBDK model cannot use any BSDK or MBDK functionality. Make sure no RTDEx or Record/Playback blocks is present in the model.
– Compile the MBDK model (for the purpose of this example, the target directory is …/work/test_sdk in System Generator).
– Once the compilation is successful, open the generated .xmp file at this location: …worktest_sdkperseus601x_sysgenperseus601x_sysgen.xmp.
This will generate the system.xml temporary file: …worktest_sdkperseus601x_sysgen__xpssystem.xml
– Copy it somewhere else since it is in a temporary folder.
– Open XSDK and create a new workspace.
– In XSDK, create a new Hardware Platform Specification, select the system.xml file, and select the bitstream and BMM files found in
…worktest_sdkxflowperseus601x_sysgen.bit
…worktest_sdkxflowperseus601x_sysgen_bd.bmm
– After the Hardware Platform Specification is created, this becomes like any other XSDK project.
For the ADP releases 6.0 or later, all libraries were compiled with Visual Studio 2008 SP1. Make sure you have Visual Studio 2008 with Service Pack 1 installed. You can download the service pack at http://www.microsoft.comhttps://nutaq.com-us/download/details.aspx?id=13276
To solve this problem, lower the clock frequency of the design or add some registers in the critical path.
After upgrading the ADP version, I get an error while compiling a project made from an old ADP version. The error are of the type ERROR:PhysDesignRules:xxxx. For example:
ERROR:PhysDesignRules:2399 – The GTXE1 comp ETH0_MAC/ETH0_MAC/V6HARD_SYS.I_TEMAC/I_EMAC_TOP/EmacBlock_l/GTP_DUAL_1000X_inst/rocketio_wrapper_inst/gtx0_rocketio_w rapper_i/gtxe1_i has POWER_SAVE[4] set to an unsupported value and must be set to 1. Please see Answer Record 39430 for more information.
Answer:
Delete the work directory to erase all files compiled with the previous version.
8-bit DDR3 SDRAM: Dedicated to the uBlaze CPU to use as a program memory either for:
a) an OS (for example, Linux)
b) a standalone C program that is too big to fit in the FPGA internal BRAM.
1G SODIMM:
Used for the record-playback module for data acquisition and storage.
It can also be used to store acquired data before being sent to the host via the RTDEx communication channel.
FLASH Memory:
Used to permanently store the FPGA bitstream, the Linux kernel, and U-boot images.
It is possible to flash the bit file to make it permanent:
+ Start the ADP CLI software.
+ Connect to the board with the command: connect your.board.ip.address (for example, connect 192.168.0.1).
+ Download your bit file to the flash using the command: fpgaflash filename.bit.
Note: The easiest way to enter the bitstream.filename is to drag and drop the Windows File Icon to the ADP CLI window after entering the fpgaflash command followed by a space.
The fpgaflash command will download the bit file and save it in the onboard flash memory.
Your bitstream should be running the next time you start the board.
This is a known issue from the license manager function that retrieves the MAC address in Windows 7, 64 bits. This happens when there are a lot of local area connections for the tunnel adapters on your computer. This can be confirmed using the “ipconfig –all” command in a command prompt. To resolve the problem, the connections have to be removed. To do so:
1) Open the device manager.
2) Select View/Show hidden devices.
3) Scroll down to the network adapters.
4) Right click and uninstall all but 1 of the tunnel adapters.
The .req file needs to be uploaded at the http://license.nutaq.com/act_server/offline/ address. From there you will get the .ans file required to continue offline installation.
Nutaq recommends the Xilinx Platform Cable USB II, model number DLC10. You can find information about it on the Xilinx web page at http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm.
No, unfortunately Nutaq does not provide board schematic.
Yes, please consult Nutaq's FMC card product sheet specifications to validate FMC requirements.
The error code is divided in three sections: the severity of the error, the module causing the error and the error itself. The following procedure illustrates how to find the error code meaning (in this case, error 0xC0640006)
Error severity: In the file %ADPROOT%sdklyt_std_libinclyr_error.h, in the ADP installation, is the enumeration Lyr_Severity. The 2 MSBs of the error code are set by the severity enumeration. Here, 0xC indicates an error (severity level is 3).
Error module: In the file %ADPROOT%sdklyt_std_libinclyr_error.h, in the ADP installation, is the enumeration Module. Bits 16 to 30 of the error code are set by this enumeration. Here, the 0x064 indicates an error from the Radio420 driver.
Error: When the error module is know, browse to the module's types headers file to find the error name. In this case, the Radio420 error enumeration is available in the fmc_radio.h file at this location %ADPROOT%sdkfmcradio_libinc in the ADP installation. Bits 0 to 15 of the error code are set by the error enumeration. Here, 0x0006 indicates that the RX DC calibration failed.
ADP releases 5.6.0 and later do not support 32-bit projects on Windows. You must compile the project with the option Release x64. If you do not have this option, you should reinstall Visual Studio with the 64-bit compiler tools.
This problem has been resolved for ADP version 6.0 and later.
For version 5.6 and earlier, this error occurred when the host had not received the specified data size and was waiting for more data.
Make sure that the MAC addresses specified in the ram get line are valid. The generic MAC addresses (host and Perseus) in the example provided with the installation must be replaced with the actual MAC addresses of your system.
Make sure there is no firewall or antivirus software running on the host computer that could impede packet transfers.
Two types of error can occur: When, in the examples, the error is “WARNING: transfer frames lost:”, it means that an RTDEx packet was lost between the FPGA and the host. Make sure the Perseus is connected directly to the host computer (no Ethernet switches external to the chassis). It is also possible that the host computer cannot handle the speed of the transfer from the FPGA. To slow the transfer, set the frame gap to a higher value. For example, #define FRAME_GAP 200000.
When, in the examples, the error is “WARNING: transfer not completed because of a small timeout”, it means that not all the expected packets were received but no packets were lost. The causes for this can be an incorrect configured RTDEx and Record/Playback cores (for example, trying to receive more packets than previously indicated in the RTDExStart function) or it can be a bad connection between the RTDEx and Record/Playback cores in the FPGA. The RTDExReceive function returns the number of bytes received, which can help you find the cause of the problem.
