Key Features:
Prototyping is easier than ever with this new 4×4 MIMO SDR platform, with 4 channels perfectly synchronized on one FPGA. Use Simulink to leverage the power of a large Virtex FPGA without writing a single line of HDL code. 70 MHz to 6 GHz on one single radio: Unlock the full performance of the AD9361 across all frequency bands.
- 4×4 in one single FPGA perfectly synchronized
- Fully integrated with Matlab Simulink and Xilinx System Generator (model-based design tools)
- AD9361 Radio Frequency Integrated Circuit (RFIC)
- Software defined up to 6 GHz and 56 MHz BW
- GNU Radio Support
- Small form factor: 215 mm x 48 mm x 290 mm
- Embedded Linux PC: connect remotely from any computer or run standalone
- Plug-and-play, with Ethernet, PCI Express and VITA-49 Radio Transport Protocol (VRT)
- Low Latency (75 µs roundtrip) and high speed (10 Gbps) PCIe interface
- QAM64 OFDM Ref Design*
*The reference design is currently available on the 1st PicoSDR Generation

70 MHz to 6 GHz on one single radio
The PicoSDR 4×4 relies on one single 70 MHz – 6 Ghz radio card, built on the agile and high-performance AD9361 Radio Frequency Integrated Circuit (RFIC), that offers the full performance on all bands frequency.
- RF 2×2 transceiver with integrated 12-DACs and ADCs
- 70 MHz to 6 GHz frequency range with integrated fractional-N synthesizers (2.4 Hz maximum LO step size)
- Supports TDD and FDD operation
- Tunable channel bandwidth: 200 kHz to 56 MHz
- Receiver sensitivity with a typical noise figure of 7 dB from 200MHz to 4 GHz and 10dB from 70MHz to 6 GHz
- 100dB RX gain control with real-time monitor and control signals for manual gain
- Independent automatic gain control
- TX OP1dB : +18dBm from 200-4000MHz and +10dBm from 200-6000MHz
- Highly linear broadband transmitter (TM3.2 20MHz-16QAM LTE signal):
- ACPR < -50dB for +10dBm and <-45dB for 0 dBm at 2.4GHz and 6GHz respectively
- EVM = 2.5% and 3% for +10dBm and <-45dB for 0 dBm at 2.4GHz and 6GHz respectively
- TX noise: =-150 dBm/Hz noise floor
- 100dB+ TX gain control with 31dB external gain control
Configurations
Rapid HIL Testing with no HDL Coding Necessary
Our fully integrated model-based design approach lets developers easily move through the model, simulation, code, hardware-in-the-loop, and real-time validation phases…iterating rapidly to refine their algorithms while benefiting from automatic HDL coding tools.

Success Stories
CorteXlab Inaugural Meeting – Oct 28,2014
Nutaq Announces the 2014 Software Defined Radio Academic US Contest Winner
Nutaq’s PicoSDR Selected By FIT/CorteXlab For Large Cognitive Radio Testbed
Videos
Cognitive OFDM
OFDM Reference Design Overview
Rapid development with Nutaq’s PicoSDR
Using the PicoSDR for 4G/5G Rapid Prototyping
Getting Started With Nutaq’s OFDM QAM64 Reference Design in 10 Minutes
Nutaq’s GNU Radio Enabled PicoSDR Embedded Solution
Introduction to QAM And Its Impact On SDR Transmission System
White Papers
Design and Implementation of Wideband Spectrum Sensing on SDR Platform With Receiver Calibration
Advanced MIMO Waveform Deployment Using GNU Radio
Using TCM Techniques to Decrease BER Without Bandwidth Compromise
Technical articles
Offloading GNU Radio Processing With FPGA Logic
Drexel Develops a Software Defined Communication Testbed Using Nutaq Radios