In this series:

In Part 2 of this blog series, we imported a pcore generated from a System Generator model into a Xilinx FPGA development platform (Nutaq’s ZeptoSDR). Like I mentioned at the end of the post, if you are using System Generator 14.5 or older, you will encounter a problem regarding the direction of the signal vector. If you don’t have this problem, you can skip directly to the ‘Port connection’ section later in this post.

Bug fix for System Generator 14.5 or older


To solve this issue, you need to modify two files: the MPD file and the cnt_sysgen_axiw.vhd of your pcore. You can access both of these files directly by right-clicking on the cnt_sysgen_axiw_0 core.

Let’s start with the MPD file:

Here’s what you should see:

There are obviously many ports defined in this file (the previously performed pcore generation also created code to use it on an AXI bus). We won’t use this functionality, however, so the only port relevant to us is gateway_out. The output port vector is defined as

[0:(8-1)], so it needs to be changed to [(8-1):0]. This is the only modification that needs to be done in this file since the other port used in our pcore is gateway_in and it only possesses a single bit. If your custom core has other signal vectors, you need to flip the vector direction for each of them. Once you’re done, you can close the file and save the modifications.

Let’s now modify the other file, cnt_sysgen_axiw.vhd:

In the .vhd file, scroll down until you reach the cnt_sysgen_axiw entity. You should see the following:

Again, there are many ports there but the only one that needs modification is gateway_out. Replace (0 to 7) at the end of the signal description with (7 down to 0). Close the file and save the changes.

Once the modifications to these two files are done, we need to refresh the IP library:

Click the button on the top left of the screen. You should see that the range of the gateway_out vector has changed.

Port connection

The sysgen_clk port is the master clock of your design. Depending on your design’s sampling rate, the value of this clock will differ. In our example, we use an internally generated 100 MHz clock in the Zynq processor, which is FCLK_CLK0 from the processing_system7_0 core.

The second port that needs to be connected is gateway_in, which will be connected to net_vcc (if you look back at our original System Generator model, you’ll see that our counter will always be enabled). After making the connections, your screen should look like this:


The port gateway_out will be connected later to Chipscope, for real-time scoping. The next step is to generate the netlist. This is easily done by clicking on the Hardware tab and selecting Generate Netlist. If you generated previous netlists for your project, I recommend that you do a Clean Netlist beforehand in order to avoid possible compilation errors.

Once the netlist generation is done, you can close your Xilinx Platform Studio project. We are now back to the PlanAhead project. The last step before adding Chipscope to our design is to run the synthesis. Click Run Synthesis in your PlanAhead project window.

In the last post of this blog series, we will add Chipcscope to our project, generate the final bitstream, and then validate it with Chipscope Analyzer. This process ensures that we correctly implemented our counter and, being generated from a System Generator model, we didn’t have to write the VHDL core for it.