Perseus 611xPowerful Yet Flexible…With A 5G Growth Strategy That Maximizes Your ROI

The TitanMIMO 5G Massive MIMO testbed has two core FPGA-based functional units:

  1. The multiple subgroups which interface with the RF front ends.
  2. The central processing engine which receives & processes the aggregated information from all subgroups.

The central processing engine has two distinct processing configurations which vary based on the number of FPGAs used for processing:

  1. Single – Uses a single, large FPGA (Perseus 6113 AMC board).
  2. Distributed – Based on a single board containing a distributed cluster of 8 FPGAs (Kermode-XV6 ATCA board).

(To see our growth strategy from the TitanMIMO-4 to a full 5G capable testbed, view our 5G Growth Strategy page.)

Subgroup FPGA Processing

In both the single & distributed FPGA central processing engine configurations, the subgroups contain a double-width Perseus 6111 AMC board. This board has a Virtex-6 LX550T and two FMC-HPC sites that will connect to the radio front-ends.

Each Perseus 6111 can support two Radio 420M boards, thus four transceivers. The Perseus 6111 serves as a processing unit as well as an enabler for the Aurora interface through the rear transition modules (RTM). The Perseus 6111 is also equipped with 4GB of SDRAM memory as well as the FPGA IP cores to read and write into this memory at very high speed. The Perseus 6111 also contains the logic to handle the radio front end's functions and set the RF parameters dynamically (frequency, bandwidth, amplification of the signal, high speed AGC, etc.)


Central Processing Engine – Single

In the case of the single FPGA central processing engine configuration, the subgroups all feed into a common master central processing engine, which is a Perseus 6113 powered by a large Virtex-6 SX475T.

Massive MIMO FPGA Configuration - Single Processing Engine

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Central Processing Engine – Distributed

To achieve a distributed FPGA central processing engine, the Perseus 6113 of the central processing engine is replaced with the Kermode-XV6. The Kermode-XV6 board presents developers with enormous power via its 8x Virtex-6 SX475T FPGAs. 

Massive MIMO Testbed - Distributed Central Processing Engine

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Key Features

  • Virtex-6 FPGA (SX475T and LX550T).
  • Real time data exchange (RTDEx) module handling PCIe and GigE for control and data exchange.
  • Support of 7x Aurora communication channels (Aurora 4x – 16 Gbps) over miniSAS connectors.
  • Control module for the Radio 420 RF front-end enabling SDR features and auto-calibration.
  • Programmable logic space for the user's algorithm.
  • Supports FPGA modules for time stamping and PPS synchronization of the data transfer.
  • SDRAM memory with record/playback module on the FPGA