In the blog post, The Kermode platform – Part 1: System and hardware overview, I introduced the hardware configuration of the Kermode platform. In this second part of the series, I describe the communication interfaces between the eight Virtex-6 SX475T field-programmable gate arrays (FPGAs) and the front and back panels.
The Kermode’s communication interfaces are designed to enable the transfer of massive amounts of data between each of the FPGAs and the external world.
Main data paths
FMC high-pin count connectors
Each of Kermode’s four front FPGAs are connected to a full FGPA mezzine card (FMC) high-pin count connector. The typical FMCs used with Kermode are either high-throughput transceivers like a 10 Gigabit Ethernet card with SFP+ or QSFP connectors or multi-channel ADC/DAC cards like the Nutaq MI125. The FMC connectors are the Kermode’s main method to input and output data to and from the system.
ATCA mesh data path
The Kermode’s main data path consists of 15 Gigabit transceivers that connect the front FPGA, rear FPGA, and the back panel zone 2 connector. Each data lane is capable of transferring up to 6.5 Gigabits per seconds, enabling a theoretical link of 97.5 Gigabits per second between each device.
As the above figure shows, each front and rear FPGA pair are connected by the GTX data path to the ATCA mesh fabric. The data path is set up in a triangular configuration. Data can be sent from the front FPGA to the Zone 2 connector, received on the back FPGA, and forwarded to the front FPGA. This configuration enables data to be shared between multiple Kermode platforms or with a CPU blade.
The ATCA fabric configuration is defined by the selected ATCA chassis. It permits the instantiation of Serial Rapid IO, PCI Express, or XAUI 10 Gigabit Ethernet links.
User IO data path
Each rear FPGA is connected to the User IO connector (Zone 3) with a 16-Gigabit transceiver-pair full-duplex bus, creating a bidirectional data link capable of 104 Gigabits per second.
In the Advanced TCA specification, Zone 3 is user-defined and is typically connected to a rear-transition module (RTM). RTMs can support PCI Express, SATA, and Gigabit Ethernet connections, either on the rear panel of the chassis or between the RTMs.
Service data paths
Adjacent FPGA data path
The adjacent FPGAs (as shown below) are interconnected by a 12-pair LVDS full-duplex bus.
Non-adjacent FPGA data path
Non-adjacent FPGAs (as seen below) are interconnected by two Gigabit transceivers.
Front and rear service data path
Each front and rear FPGA pair can use a dedicated Gigabit transceiver to exchange data and commands, as shown below.
For additional information on the Kermode and its data paths, see the Kermode XV6 platform brochure.