System Generator is a high-level development tool from Xilinx and is fully integrated with MATLAB Simulink for the design of high-performance DSP systems targeting FPGAs. In our Tips and Tricks blog series, we looked at common techniques and approaches to help you get the most out of this versatile tool and avoid common problems.
Here’s links to the five posts in this series:
- Xilinx System Generator tips and tricks – Part 1: An introduction
- Xilinx System Generator tips and tricks – Part 2: HDL code reusability
- Xilinx System Generator tips and tricks – Part 3: Using MATLAB M-function for easy state machine coding
- Xilinx System Generator tips and tricks – Part 4: Understanding timing issues
If you missed some of the posts the first time, or you are just starting out with System Generator, here’s a recap of this practical and very helpful series.
A recap of Part 1: An introduction
In Part 1, we introduce System Generator and discuss its benefits by looking at a GSM digital down-converter example model. We use this model to quickly generate the associated HDL code or bitstream.
A recap of Part 2: HDL code reusability
In Part 2, we look at how you can create custom blocks in the MATLAB/Simulink environment by reusing HDL code. In the post, we select the System Generator Black Box primitive, add the referenced VHDL code, and configure the output interfaces.
A recap of Part 3: Using MATLAB M-function for easy state machine coding
In Part 3, we show how System Generator provides direct support the MATLAB language via the MCode block. In the post, we implement and test an initialization finite state machine for a moving average filter.
A recap of Part 4: Understanding timing issues
In Part 4, we discuss using System Generator to address a common issue faced by users: timing issues. The post explains how to identify timing issues and the possible causes behind them.
A recap of Part 5: Simple methods to fix timing issues within System Generator
In Part 5, we work with System Generator to resolve the timing issues. The post provides a walkthrough on the following procedures:
- Identify the failing paths
- Add registers to cut the critical paths
- Set Xilinx block optimization options