- Using the 4 GB DDR3 memory to record short bursts
- Using the internal 200 GB solid-state drive (SDD) (or larger external drive) to record longer bursts
In this post, we discuss the 5 factors to consider when selecting a storage source as well as investigate further the option of using the 4 GB DDR3 memory.
The DDR3 record path is highlighted in the following diagram:
1. Location(s) where real-time preprocessing is performed (PC and/or FPGA)
In some applications, the purpose of capturing and storing a raw RF signal is to process it at a later time using analysis tools that are not capable of operating in real time on the high-bandwidth signal. The DDR3 record tools are ideal for these cases; their high throughput enables them to capture raw, unprocessed I/Q samples out of the RF receiver (we'll cover throughput considerations in more depth later on).
In other applications, some digital signal processing is applied to the I/Q sample streams prior to being stored in the DDR3. Reasons for doing this can include leveraging the FPGA to implement computational intensive signal analysis algorithms that would otherwise take several seconds or minutes on a PC application to perform. Or, you could be designing an entire real-time system in the FPGA but want to capture the output of a processing block for debugging purposes.
In both situations, the DDR3 record tools are suitable. The only limitation to consider is that the PC is not part of the real-time path. Signal processing algorithms must be implemented in the FGPA if they are to be tested for real-time operation.
2. Interfaces through which the signal travels before being stored (e.g. DDR3, PCIe, SSD, etc) and their respective throughput limitations
Nutaq provides a record/playback FPGA module with the RF Wideband Digitizer. The module includes a low-level driver and a user interface between the DDR3 memory and the FPGA. This recording interface has the highest data throughput (when compared to the 200 GB SSD option).
The maximum data throughput measured between the FPGA and the DDR3 is 5.7 GBps. This throughput rate lets you store a lot of data per time unit. Of course, at this rate, a 4 GB DDR3 SODIMM will get completely filled after only 720 milliseconds. That being said, 720 milliseconds is more than enough time for many applications that use multiple sensors to record for a short period after a precise event occurs.
3. Is real-time pre-processing applied on the signal before the samples are stored?
There is an equation that links the DDR3 interface throughput with the sampling rate used by the I and Q analog-digital converters (ADCs) and the number of channels. Only one RF front-end and one I/Q channel is shown in the above diagram, but it is possible to alter the architecture of the digitizer to support multiple front-ends(see PicoDigitizer-125 series).
In single-channel applications (PicoDigitizer-250), the DDR3 interface throughput is 5700 MBps, which leads to a maximum sampling 2850 MSps (I/Q combined) when raw I/Q samples (16 bits each) are fed straight to the DDR3 FPGA record module. This isn’t a bottleneck since it's much higher than the system’s maximum sampling rate. But in a multi-channel application (on the PicoDigitizer-125 series for instance), 22 channels of data (125 MHz, 16 bits per sample) of an MI125-32 could be recorded in parallel using the DDR3 interface.
If real-time pre-processing is applied on the signal before the samples are stored, we must rather look at the throughput limitation in terms of data rate at the signal processing block output, rather than in terms of raw I/Q samples. It is possible to increase the number channels recorded with the MI125-32 (PicoDigitizer-125) by pre-processing the signal in real time on the FPGA prior to storing the samples in the DDR3. A decimation filter, for example, is a very simple kind of real time pre-processing.
4. Sampling rate
Another way of increasing the number of channels captured and stored with the DDR3 interface in a PicoDigitizer-125 multichannel system is to sample at a slower rate. For instance, 32 channels of data (16 bits per sample) of an MI125-32 could be recorded in parallel using the DDR3 interface if the ADC sample rate is slowed down to 85 MSps.
5. Bandwidth of the RF signal of interest
Both approaches (decimation filter or reduced sampling rate) result in information loss (in this specific case, reduced bandwidth). Sometimes, however, this is a reasonable trade-off when recording higher numbers of channels. The Nyquist theorem establishes a relationship between the ADC sampling rate and the captured RF signal bandwidth: the sampling rate (I/Q combined) must be twice as high as the signal bandwidth. The WR8G/20G has an instantaneous bandwidth of 100 MHz. Hence, the I and Q ADCs must run at least at 100 MSPS each. Alternatively, a different RF front-end with a narrower bandwidth can be used. By default, the PicoDigitizer-125 runs at 125 MSPS (max) and the PicoDigitizer-250 runs at 250 MSPS. Slowing down the ADCs will in increase the maximum recording duration or provide the capacity for more channels.