When we talk about FPGA-based filtering, most of us think about implementing a finite impulse response (FIR) filter. However, FIR filters take resources. With larger FPGAs, this is not a big deal. But I’ve faced situations where my FPGA design couldn’t fit because of the additional resource consumption of the FIR filters. At this point, other options need to be considered and cascaded integrator-comb filters are a good one.

CIC filters were introduced to the signal-processing community by Eugene Hogenauer over two decades ago. They are computationally efficient implementations of narrowband low-pass filters, which make them well-suited as anti-aliasing filters prior to decimation and anti-imaging filters for interpolated signals. Both applications are associated with modern wireless systems and delta-sigma analog-digital (A/D) and digital-analog (D/A) converters. Because their frequency-magnitude-response envelopes are sin(x)/x-like, CIC filters are typically either followed or preceded by higher-performance linear-phase low-pass tapped-delay-line FIR filters, whose task is to compensate for the CIC filters’ non-flat pass-band:

This cascaded-filter architecture has valuable benefits (reduced complexity and reduced power consumption in hardware) but the crucial benefit of using CIC filters is that they require no multiplication. CIC filters are derived from the notion of a recursive running-sum filter, which is itself an efficient form of a non-recursive moving averager. Let’s recall the D-point moving-average process in the time domain:

The z-domain expression is as follows:

which gives us the following transfer function:

                The next step toward understanding CIC filters is to consider an equivalent form, the recursive running-sum filter:

with the following transfer function:

The transfer functions of both approaches are relevant since it shows that both are equal to each other. However, the recursive running-sum filter has the advantage that only one addition and one subtraction is needed per output sample, regardless of the delay length D. That brings us to the fact that if we remove the 1/D factor, we get the CIC filter’s difference equation:

with its transfer function being:

By setting  and using Euler’s identity, we can write:

If we ignore the phase factor in the equation above, the ratio of sin() terms can be approximated by a sin(x)/x function. This means that the CIC filter’s frequency magnitude response is approximately equal to a sinc function centered at 0 Hz. Here is an example of frequency magnitude response of a 1st-order, D=8, decimation filter:

Figure 1: Magnitude response of a 1st-order, D = 8, decimating CIC filter: before decimation; aliasiing after R = 8 decimation 


                The spectral band, of width B and centered at 0 Hz, is the desired passband of the filter. A key part of CIC filters is the spectral folding that takes place after decimation. The lowest figure above is showing the aliasing created after decimation. The most common way to improve the anti-aliasing is to increase the order of the CIC filter by adding stages:

Figure 2: 3rd-order CIC decimation filter structure, and magnitude response before decimation when D = R = 8 [1]

                Because there are three stages in the cascade, the overall frequency magnitude response will be the product of their individual response:

The price to pay for the increased performance is additional hardware adders and passband droop. Even so, this multistage implementation is commonly used in commercial integrated circuits.

For more information on CIC filters, I highly recommend you read the following article on the subject: http://www.embedded.com/design/configurable-systems/4006446/Understanding-cascaded-integrator-comb-filters


[1] Lyons, R. (2005, March). Understanding cascaded integrator-comb filters. Retrieved from http://www.embedded.com/design/configurable-systems/4006446/Understanding-cascaded-integrator-comb-filters