In this series:



In our last blog post, we used a demo application included with Nutaq’s Model-Based Design Kit (MBDK) to validate the software installation and our system’s configuration. The objective of this post is to describe our project and break it down into smaller, more manageable, implementation phases.

The project

The final goal of the project is a system with the functionality shown in Figure 1. The system consists of a transmitter and a receiver. The transmitter is looped back to the receiver by a wire. A digital signal is generated on the host PC and is sent to the FPGA by the real-time data exchange (RTDEx) channel for modulation. RTDEx is Nutaq’s IP core for data exchange between a host PC and the FPGA.

Once modulated, the signal is sent to the digital-analog convertor (DAC) for transmission. The transmitted signal is looped back into the analog-digital convertor (ADC) to be digitized again. Once digitized, it goes through a demodulation phase and is sent back to the host by the RTDEx channel.

Figure 1: The project's functional block diagram

Figure 1: The project’s functional block diagram

In this project, we also want to be able to introduce new blocks for additional signal processing before modulation.

Dividing the project into phases

The project will be divided into four phases. This approach lets us troubleshoot any problems while the system still has a low complexity (i.e. before we augment it with additional blocks). Once each phase is done, there is a testing phase where the system is simulated. If the simulation works, we move on to the next phase. At no point during these phases will the actual hardware be used; the system is going to be tested only by simulation.

Phase 1

In Phase 1, we will generate a digital signal on the FPGA using a direct digital synthesizer (DDS) and send it directly to the ADC. The signal will then be physically routed to the ADC by the loopback wire. We’ll use Chipscope to plot the signal and check its integrity. Once we receive the exact same signal on the chipscope as generated by the DDS, we can progress to Phase 2.

Figure 2: Functional block diagram for Phase 1

Figure 2: Functional block diagram for Phase 1

Phase 2

In phase 2 we will simply add an AM modulation block at transmission and its respective demodulation block at reception. We will still use the DDS and the chipscope to generate and plot the data.

Figure 3: Functional block diagram for Phase 2

Figure 3: Functional block diagram for Phase 2

Phase 3

In Phase 3, instead of using data from the DDS we will receive data from the host PC via Gigabit Ethernet. We will also send the data back to the host PC and use the PC for plotting instead of Chipscope. Finally, we will replace the signal source and signal sink to get closer to the target system.

Figure 4: Functional block diagram Phase 3

Figure 4: Functional block diagram Phase 3


Phase 4

In Phase 4, we will include single sideband modulation in the PC.  This modulation will precede the AM modulation done in the FPGA. The goal of performing modulation in both the PC and the FPGA is to offload processing effort from the PC to the FPGA.


The goal of our project is to design a modulating system that uses a PC for single sideband modulation and an FPGA for AM modulation. We explained how we split the project into four phases to simplify troubleshooting activities. In the next blog post, we will describe our experience implementing the project and comment on any problems that we encountered (and explain how we fixed them).