CorteXlab, located in Lyon, France, integrates software-defined radio (SDR) nodes to offer a remotely accessible development platform for distributed cognitive radio applications. CorteXlab selected Nutaq’s PicoSDR for their large cognitive radio testbed. The PicoSDRs form a large set of heterogeneous SDR nodes, each in a 2×2 or 4×4 multiple-input/multiple-output (MIMO) configuration.
In November 2013, Nutaq visited CorteXlab to provide on-site support following the delivery of 18 SDR nodes. The agenda included the following objectives:
- Validate the PCI Express (PCIe) Real-Time Data Exchange (RTDEx) streaming link
- Update the existing field-programmable gate array (FPGA) design to use PCIe
- Review the GNU Radio plug-in architecture used in Nutaq’s Advanced Development Platform (ADP) 6.4
Day 1: Validate the PCIe RTDEx streaming link
On day 1, we used Nutaq’s standard FPGA example application to validate the PCIe streaming interface between the PCs and the PicoSDR nodes.
Figure 1: Block schematic of the standard FPGA example application included in version 6.4 of Nutaq’s ADP
We used Xilinx Platform Studio (XPS) to compile the design and generate a bitstream to flash the PicoSDR platforms. We then connected a PCIe 4x cable to the external PCIe connector on the back of the PicoSDR platform. The other end of the cable was connected to the industrial PCs on the radio testbed.
The external PCIe connector enables 750 MBPS PCIe streaming to the PC (approximately 187.5 MHz of IQ bandwidth). Without the PCIe option you are limited to 120 MBPS Gigabit Ethernet streaming (approximately 30 MHz of IQ bandwidth). This 30 MHz of IQ bandwidth can become a bottleneck – there are two (or four) transceivers with 28 MHz of bandwidth in the system but only the PC bandwidth for streaming to one. Adding the PCIe option gives your platform longevity, enabling it to be used in future projects with demanding bandwidth requirements.
Nutaq’s PC drivers and FPGA cores provide an abstraction level from the streaming media. In our FPGA design, we simply selected the PCIe option from the Nutaq RTDEx drop-down menu.
Figure 2: Setting the RTDEx core parameter to PCIe in System Generator (the same option is available in XPS designs)
In GNU Radio, we could simply select the PCIe option from the Nutaq RTDEx drop-down menu and test the streaming by running the provided example.
Figure 3: Setting the RTDEx API parameter to PCIe in GNU Radio (the same option is available in C/C++ applications)
Day 2: Update the existing FPGA design to use PCIe
On day 2, we worked on migrating an existing ADP 6.3 802.15.4 design to ADP 6.4. The 802.15.4 protocol was entirely implemented in the FPGA from a Xilinx platform studio project. We started by comparing the Nutaq ADP 6.3 and 6.4 reference designs with the Beyond Compare utility in order to identify anything that might have changed. After applying some minor changes to the 802.15.4 design to make it compatible with 6.4, we swapped its RTDEx Gigabit Ethernet streaming interface with the RTDEx PCIe to benefit from the highest throughput and lowest latency the PicoSDR platform can offer. This work was quite straight-forward. Thanks to the provided GigE and PCIe .mhs files, we could easily compare the default GigE and PCIe designs and apply those changes to our 802.15.4 project file.
Day 3: Review the ADP 6.4 GNU Radio plug-in architecture
On day 3, we installed GNU Radio 3.7.1 and the Nutaq GNU Radio plug-in for ADP 6.4. A carrier board must be instantiated in the GNU Radio environment. The carrier block specifies the platform’s IP address and carrier type. With the PicoSDR platform, the Perseus Carrier block must be used.
Figure 4: Nutaq carrier block for GNU Radio
The Radio420 blocks configure the reception and transmission path. These blocks are used to configure the different parameters of the Radio420, including RF frequencies, data rate, analog gains, and filters. When a Radio420 in a double-stack configuration (MIMO) is used, two RX and two TX Radio420 blocks must be instantiated
Figure 5: Nutaq Radio420x blocks for GNU Radio
RTDEx sink and source blocks are available for easy and direct data transfer between the host application and the FPGA design. Each RTDEx channel implementation and its counterpart in the FPGA can be seen as a data pipe with a flow control mechanism.
Figure 6: Nutaq RTDEx blocks for GNU Radio
Custom register blocks can be used to read and write data within the FPGA design. The write operation can be triggered by a variable or by a data stream. These blocks enable the host application to dynamically control the FPGA.
Figure 7: Nutaq register blocks for GNU Radio
Finally, the day ended with this picture, taken in the control room next to the RF experimentation room, in front of a stack of PicoSDR boxes filled with SDR units to be installed in CorteXlab’s large cognitive radio testbed.
Figure 8: On the left is Tristan Martin, Nutaq field application engineer, holding a PicoSDR 4×4 platform. On the right, Dr. Abdelbasset Massouri, R&D Engineer at CorteXlab, holding a PicoSDR Embedded. Behind them, a PicoSDR 2×2 and 18 boxes containing the recently delivered PicoSDRs for use as part of a heterogeneous testbed.