In this series:

Part 2: Record and Playback core implementation – Record Mode

My previous blog post discussed the common use cases of the Record and Playback FPGA module. In this post, we follow up by discussing its implementation and the main features of record mode.


The Record and Playback module is controlled by a host PC library and AXI bus-based registers. It interfaces with the Perseus FMC carrier DDR3 SODIMM (1 GB or 4GB).

The following diagram illustrates the data flow within the module:

Figure 1: Record - Playback FPGA Core

The Record and Playback module has four modes of operation:

• Record mode: Receives data from the user logic and stores it in memory
• Playback mode: Reads data from memory and outputs it to the user logic
• Memory to host mode: Interfaces with the RTDEx module to send data from the memory to the host PC
• Host to Memory mode: Interfaces with the RTDEx module to receive data from the host PC and store it in memory

Note that the Record and Playback module can only be used in one mode at a time.

Record mode

When the module is in record mode, the user can:

• Record data to DDR3 memory
• Record data from different sources (on different ports)
• Record data for a finite number of samples (the transfer size in bytes must be specified)
• Trigger a recording from an external signal (user logic or the FMC front panel) or from software (Record and Playback library function call)
• Offset the start of a recording to compensate for a delay between the trigger and the event to record

The maximum tested bandwidth of record mode is 5.7 GBytes per second.
The following diagram illustrates the data flow within the record module:

Figure 2: Data flow within the record module

Data recording

The record module uses an array of input ports in order to record data from different sources. The number of record ports used and their width are user-configurable. The following table shows the valid combinations for these two variables:

Table 1

Note: All the ports must have the same width because the acquisition packer FIFO packs its input data on 256 bits. The product of the number and width of these ports cannot exceed 256.

The data received from all the channels is stored contiguously in memory. For example, when recording on 4 channels of 16 bits, the resulting data in memory will look like the following table (ChA – 0 means Channel A sample 0):

Table 2

Record triggering and data retrieval

The record mode enables the use of an external trigger, which can be a physical signal from outside of the data acquisition system or a signal generated by data processed within the user logic.

When in record mode, the DDR3 memory is used as a circular buffer. As soon as the FPGA core is initialized in that mode, data from the user logic is continuously stored in the memory until the trigger signal is received by the FPGA core. When record is triggered, the core will save the exact address in memory at which the trigger signal was received (enabling the user to retrieve the data corresponding to the signal). The core will stop storing data when the specified record length is reached (preventing the overwriting of data in the circular buffer).

The triggering system has other features and benefits:

• Using the memory as a circular buffer permits the user to retrieve data acquired prior to the trigger signal. It is possible to go back as far as the DDR3 size will permit.
For example, when acquiring a 16-bit signal at 100 MSPS on one channel (200 MBytes/s) on a 4 GByte DDR3, the memory will hold 20 seconds of data. This means that the user could retrieve acquired data as far back as 20 seconds prior to the trigger signal.
• The trigger mechanism can be delayed in order to record an event occurring some time after the signal trigger. For example, the user wants to record a 10 ms event and knows that a signal is always generated 100 ms prior to the event. By delaying the trigger by 100 ms, the user will be able to store only the 10 ms event instead of the full 110 ms. Reducing the amount of recorded data is useful with high-throughput acquisitions where the memory fills up quickly.

Figure 3

To retrieve the data from a host PC, the user needs to perform a memory to host transfer with the help of the RTDEx module. The memory to host mode of the Record and Playback module reads data from the memory at a specified address (for example, the trigger address) and sends it to the host PC through via RTDEx.


As we have seen, the record mode of the Record and Playback module has many helpful features. Part 3 of this blog will concentrate on the module's data playback implementation.