In this series:
- A real-time processing system for dual-comb spectroscopy: Part 1
- A real-time processing system for dual-comb spectroscopy: Part 3
In my previous blog post, I explained dual-comb spectroscopy and how to compensate for instabilities by using post-processing algorithms. In this post, I discuss a real-time processing and averaging solution implemented on the Xilinx ML605 development platform and the MI250 FGPA mezzanine card (FMC) from Nutaq.
Acquisition of the IGM and reference signals
As described in the previous post, the reference system produces four analog signals. These signals, as well as the interferogram (IGM) signal, must be digitized using analog-to-digital converters. An acquisition card with at least five ADCs is required. Instead of using one ADC card with mulitple channels, several ADC cards in parallel could also be used. However, multiple cards increases system complexity and the inter-card synchronization is harder to manage. For these reasons, the MI250 FMC with its eight 14-bit ADC was chosen as the acquisition card.
The MI250 can run up to 250 MHz and its effective number of bits (ENOB) is higher than the analog signals sampled. Only 100 MHz of bandwidth is required because of the repetition rate of the frequency comb. As the MI250 is an FMC, it requires a connection to an FPGA carrier board with an FMC connector.
FPGA carrier board
The ML605 is a development board from Xilinx. It has a Virtex-6 FPGA that can handle large, high-speed signal processing algorithms. The board has several external communication links, including UART, Ethernet, PCIe, USB, and SFP. Only the UART protocol was implemented in the final solution due to its simplicity. While the UART protocol is perfect for controlling the algorithm parameters and reading a few status flags, due to its low bandwidth, it is not the best solution for data transfer.
The ML605 has DDR3 SODIMM memory with a bandwidth of several GB/s. This memory matches the prerequisites of the real-time averaging part of the processing system, which requires several bytes to be written and read at a 100-MHz rate.
System architecture and algorithm implementation
The real-time correction of the IGM, based on the four reference signals, must be performed continuously in the FPGA. Also, the corrected IGMs must be averaged. Even if the IGMs are corrected using the reference signals, an offset can exist on their sampling grid and phase. To coherently average the IGMs, these parameters must be the same for every IGM.
Figure 1 shows the system architecture implemented in the FPGA logic.
Figure 1: FPGA system architecture
The MI250 block configures the MI250 FMC at startup and receives the digital streams from the ADC. It provides an interface to access the MI250's ADC data.
The Correction block receives the IGM and its four reference signals from the MI250 block for correction. Once corrected, the IGMs are sent to the Alignment & Averaging block. This block reads the averaged IGM located in the DDR3 memory, performs a partial cross-correlation to retrieve the offset and phase differences, and adds the newly corrected IGM to the averaged ones.
The DDR3 Manager acts as very large first-in first-out (FIFO) memory and is developed around Xilinx Memory Interface Generator (MIG) core.
The UART block is used to configure every other block. It decodes commands from a remote computer. Read and write register commands can be received as well as probe commands.
The Probe block acts like a configurable oscilloscope. It can record waveforms from the Correction block algorithm or signals from the Alignment & Averaging block. Then, the data is transferred to the computer for analysis. The block ensures that the FPGA algorithm is correctly configured and optimized for better performance. It can also be used for debugging.
Once an acquisition is complete, the averaged IGM is sent to the host computer through the UART block. This may take a few minutes due to the low throughput of the UART.
The entire project was developed with Xilinx ISE and ModelSim was used for FPGA simulation. When implementing algorithms on an FPGA platform, a lot of time can be spent on its interfaces. A few months were spent on the UART, MI250 and DDR3 interfaces to make sure they were working properly and had the desired behavior.
The real-time correction and averaging system works as expected and is able to perform very high signal-to-noise ratio (SNR) measurements. The project could be enhanced by having the UART block replaced by a high-speed communication link.
Nutaq provides an MI250 reference design for the ML605 board. The reference design includes all the logic for controlling the FMC and makes the ADC data available in the FPGA (it doesn't support the other ML605 interfaces, however).
In my next blog post, I will explain how using Nutaq’s Perseus Virtex-6 FPGA carrier board instead of the ML605 could have sped up my development time.