Modern communication standards like ZigBee (IEEE 802.15.4) have heavy processing power requirements. ZigBee is the standard protocol adopted by the French Equipex Future Internet of Things (FIT)/CorteXlab organization in their research of providing a testbed for cognitive radio. In the context of this development, they needed to provide a platform that would be able to switch between three different IEEE-compliant PHY layer options.
To achieve the required flexibility and processing power, the researchers turned to Nutaq’s software-defined radio (SDR) solutions. The PicoSDR, powered by a Virtex-6 field-programmable gate array (FPGA) and equipped with the Radio420X RF front-end, was chosen. For the full story, see https://nutaq.com/news/nutaq-picosdr-selected-fitcortexlab-large-cognitive-radio-testbed.
This blog post provides a short introduction to the software and hardware architecture that will fully satisfy the requirements for implementing the targeted PHY layers in order to realize the testbed.
The PicoSDR architecture
The PicoSDR platform is comprised of a highly flexible FPGA mezzanine card (FMC) radio front-end (the FMC Hardware in Figure 1) connected to the FMC FPGA core equipped with a Virtex-6. As depicted in Figure 1, it includes an IP core that implements a high-bandwidth, low-latency Gigabit Ethernet (GigE) or PCIe link between the platform and a host PC.
Figure 1: The PicoSDR development platform architecture
The real-time data exchange (RTDEx) IP core provided by Nutaq optimizes data transfers by providing a direct pipeline for the data to flow between the FPGA and a PC, thus bypassing any intermediaries. The RTDEx IP core is therefore a powerful tool for communication with a host device at a high bandwidth and low latency.
The full mechanism to control the radio and to provide a direct data path between the board and the RF front-end is also provided. A soft processor core, the MicroBlaze, is used to control this mechanism and issue commands from the PC to the PicoSDR (for example, altering the sampling rate of the A/D or D/A converters). The MicroBlaze is provided with a reference design included with the platform. The central command engine (CCE) is part of an API enabling the host machine to issue commands that alter the FPGA state or change the parameters of the FMC radio.
Along with this powerful architecture, the PicoSDR supports three types of development workflows:
- Board Support Development Kit (BSDK): Enables HDL design and provides lots of flexibility.
- Model-Based Design Kit (MBDK): Allows the developer to use Simulink blocks when designing the FPGA and generates the HDL required to program it. This workflow saves a lot of time and offers flexibility.
- GNU Radio: A model-based approach that can be used for programming from the host PC.
With all these tools and workflows included with the PicoSDR, the Equipex FIT/CorteXlab engineers saw a match with their project of constructing a testbed for cognitive radio. The Virtex-6 FPGA will give them the processing power required by MIMO-OFDM algorithms and the configuration of the ZigBee protocol, and the highly configurable architecture of the PicoSDR will provide a solution to implement and select three different PHY layers on the same platform.