The MI125 FPGA mezzanine card (FMC) has analog-digital converters (ADC) that provides 16 channels, 14-bit precision, and a sample rate of up to 125 MHz. Figure 1 shoes the clock distribution circuit.

Figure 1: Clock distribution circuit diagram  (from the MI125 User’s Guide)

Figure 1: Clock distribution circuit diagram (from the MI125 User’s Guide)

As shown in Figure 1, the MI125 ADCs are driven by a clock switch that has 4 different clock choices:

  • 125 MHz local oscillator
  • External clock front connector
  • Clock from the master MI125 card (when used in double-stack 32 channels configuration)
  • Clock from the carrier board

A customer using the MI125 FMC with the Perseus 6010 reference design asked us how to drive the ADCs from the FPGA’s clock. This blog post answers this question by providing a complete walk-through on modifying the default reference design.

FPGA clock

The FPGA clock can be useful in some situations. The MI125 FMC does not have an internal phase-locked loop (PLL). It only has a low-jitter oscillator fixed at 125 MHz. To operate at a different frequency, its external clock connector can be used but this requires an additional hardware module. By using the FPGA clock, the internal mixed-mode clock manager (MMCM) components of the FPGA can be used to generate a wide range of frequencies. Furthermore, an external LVDS or LVCMOS clock reference can be used to generate the clock.

Driving an ADC with an FPGA clock has its drawbacks, however. The clock generated by an FPGA will have a lower jitter performance than a standard oscillator or analog PLL. The jitter can be few tens of picoseconds up to many hundred of picoseconds and can greatly affect the performance of the ADCs. Driving ADC clock input from the FPGA clock can be useful due to its flexibility in the development phase of a project but for a final high-performance system, an external analog clock generation module is highly recommended.

FPGA clock implementation

On the MI125, it's possible to clock the ADCs with a clock provided by the carrier board directly through the FMC connector. The clock is routed from the carrier board to the MI125 clock switch by the FMC’s BIDIR CLK3 LVDS pins.

On the Perseus board, two clock sources can drive the FMC BIDIR CLK3 pins (as shown in Figure 2).


Figure 2: Perseus clock scheme

Figure 2: Perseus clock scheme 

There is a clock switch for selecting either the FPGA pins or a clock from the AMC backplane of the Perseus. In the current case, the FPGA pins need to be selected. The clock switch selector is connected to the Perseus FPGA’s AU16 pin. In the default MI125 reference design, this pin is already mapped and connected to the Perseus Register core.

The CLK_CTRL status register section in Appendix A of the Perseus User’s Guide explains that this signal can be driven by accessing bit 10 of register 0x70000004 in the MicroBlaze processor. By default this bit is set to 0, which is the value for selecting the FPGA pins to drive the FMC BIDIR CLK3.

Figure 2 (as well as the FMC Connector table in the Pin Assignments section of the Perseus User’s Guide) shows that the FPGA pins which drive the FMC BIDIR CLK3 are the LVDS pair AY14-AY13. The following entry can be added to the .ucf file to map this pair.

It is possible to modify the current clock_generator instance (clock_generator_0) to add a new clock output port. The clock_generator_0 instance uses the 200 MHz reference clock of the Perseus board to generate a few clocks for the FPGA design. For example, a new 100-MHz clock can be generated by configuring the CLKOUT4 parameters.

Figure 3: Modifying Clock Generator Instance

Figure 3: Modifying Clock Generator Instance

The new clock can be connected to the FPGA pin by modifying the project's .mhs file.

The bitstream can be generated with the new project configuration. Once its generation is successfully completed, the bitstream can be programmed using iMPACT.

To perform an acquisition using the new FPGA clock, the record CLI script can be modified.

This configures the clock switch on the MI125 to select the clock from the carrier board (FMC BIDIR CLK3) for operating its ADCs. To confirm that the FPGA clock has been used as expected, a 1 MHz signal can be connected to the MI125's channel input.  If the 100 MHz clock generated by the FPGA is used, the recorded signal should have 100 samples for each period of the sinusoidal waveform. It is normal for the acquisition's signal-to-noise ratio (SNR) to be lower than when using the 125-MHz internal oscillator since the FPGA output clock has a higher jitter.

Using an external reference

To synchronize multiple acquisition systems together, a shared reference clock is often distributed to all the platforms. For the Perseus board with the MI125 FMC, the shared reference can be connected to the Trigger Input of the MI125. The clock must be a LVCMOS 2.5V signal.

Also, the reference clock can be connected to the Mestor Expander connector. These connector pins are directly routed to the FPGA. A LVCMOS 2.5V or LVDS 2.5V signal can be used. The .ucf file must be configured accordingly for the signal standard being used. It is recommended to use the Mestor Expander pins that are connected to FPGA clock-capable pins since they have a dedicated path to the clock components inside the FPGA. The FPGA pins connected to the DPIO 0, 7, 13 and CLK pairs are all clock-capable inputs.

External reference implementation

In this implementation example, the external trigger of the MI125 FMC will be used as an input reference for generating a custom clock inside the FPGA. This clock will be used by the MI125 ADC in the same way as described above in the FPGA Clock Implementation section.

In the .ucf file, clock constraints must be added to describe the input signal.

These new lines tell the compiler that the i_TriggerInFromIOBottom_p signal is a 10-MHz clock and to use it as a clock even if the trigger input is not on a clock-capable pin.

This input trigger goes into the lyt_axi_mi125 core located in the fpgaNutaq_ip_corespcoreslyt_axi_mi125_v1_00_a directory. The input trigger can be disconnected from its current logic and a global clock buffer can be instantiated instead.

Once the lyt_axi_mi125.vhd modifications are done, the o_TriggerToFPGA_p port of the axi_mi125_bottom instance can be used as a clock input of a clock_generator core.

Figure 4: Adding a New Clock Generator Instance

Figure 4: Adding a New Clock Generator Instance

The 10-MHz input clock frequency must be specified as the CLKIN frequency and the desired output frequency clock can be entered for the CLKOUT0 port.

In the .mhs file, the new clock_generator instance will be present and its input and output ports can be connected to the MI125 trigger and output clock pins as shown below.

Once it’s done, the bitstream must be regenerated. It can be tested using the same process as previously explained. This will enable you to synchronize a few acquisition systems together and generate a custom clock frequency in the prototyping phase of a project without requiring an external clock generator module.