Multi-channel data acquisition systems (also referred to as DAQ) are scientific or industrial instruments that digitally process “real world” information acquired in real-time from a number of sensors. DAQ systems sometimes have to work with just a handful of signals, but in other cases may have to work with a very large number of them. In almost all applications, the timing relationship between signals is of the utmost importance and must be preserved and accurately measured. This post provides an overview of some of the design practices that should be used in DAQ systems to ensure that timing information between channels is preserved during the acquisition process.


Timing Is Everything


DAQ systems use a number of analog-to-digital converters (ADCs) to digitize the signals connected to their analog inputs. Usually the variation in amplitude of each individual signal is what the DAQ system will analyze and process, but sometimes valuable information is also contained in the timing relationship between those signals. For example, this is the case for direction finding systems, which measure the phase difference between identical radio signals received from two different antennas, or in positron emission tomography (PET) scanners, where the difference in time-of-arrival (TOA) between two emitted photons is measured.

The type of algorithm performed by DAQ systems to measure the timing relationship between channels is specific to each application, but in all cases these applications assume that the timing relationship between channels will be preserved during the acquisition process.

DAQ systems must take a certain number of precautions to ensure that the timing relationship between channels won’t be altered by the physical configuration of the system, or during the analog-to-digital conversion (ADC) of signals from multiple channels.


No Time Lost


One of the fundamental ways to ensure that the inherent timing information between channels is preserved during the acquisition process is to capture those signals using a common sampling reference. This is accomplished by simply clocking all ADCs from the same clock source. Since all signals are digitized synchronously, the DAQ system only has to keep track of the moment when each set of simultaneous samples is captured. This establishes an absolute time reference from which relative timing information between channels can then be extracted.

This method is relatively straightforward and is how most analog-to-digital sections of DAQ systems operate. But doing this properly is not necessarily trivial, especially when working with signals operating at relatively high frequencies. Even though the ADCs of a DAQ system are clocked from a common clock source, it is nevertheless possible to acquire signals where the timing information between channels has been altered during the conversion process. Consider the following configuration where two signals are simultaneously digitized by two ADCs:

 configuration of a DAQ system where two signals are simultaneously digitized by two ADCs

One would expect that since both ADCs are clocked from the same source, they would be clocked at exactly the same time. This is not true in this case. What should be taken into consideration is the fact that electrical signals travel at a fixed (but very fast) speed of approximately six inches per nanosecond (one billionth of a second) in the traces of an electronic printed circuit board (PCB). In the example above, there’s a difference in length of six inches between the trace for the clock signal connected to ADC #1 and the one connected to ADC #2, which means that the clock signal will reach ADC #2 one nanosecond after it reaches ADC #1. This may not appear like much, but for ADCs modules such as Nutaq’s MI-250, which operates at 250 MHz (a sampling period of 4 nanoseconds), this would represent an error of one quarter of a sampling period between channels, which is very significant. This also means that if identical signals were connected to Input #1 and #2, the DAQ system would consider that there is a delay of one nanosecond between those signals, when in fact there is none.

There’s not much that can be done to eliminate the inherent delay in signals traveling in the electrical traces on the surface of a PCB. However, it’s possible to ensure that the same delay exists for all signals that travel from similar sources to similar destinations. This process, called trace length matching, is shown in the following figure, which illustrates the main signal paths on an ADC module such as Nutaq’s MI-250.

 Trace Length Matching_main signal paths on an ADC module such as Nutaq’s MI-250

The signal from the clock source (either internal or external) is replicated by a clock distribution buffer that creates multiple copies of the clock signal that are perfectly synchronized. All signals of this group (circled by a dotted loop in the diagram) share the same trace length and reach the ADCs at the same time. On Nutaq’s ADC boards, trace lengths are usually matched within 1mm (approximately 1/25th of an inch). Trace length matching is also required for the signal going from the input connectors to the inputs of the ADCs so that the timing relationship between those signals is not altered.

Also, as noted in the figure above, care must be taken to match the length of the cables connecting the signals from the analog front end to the ADC module in order to minimize the difference in delay between channels.


Clocking and Synchronization at the System Level


As we’ve discussed, preserving the timing relationship between channels in a DAQ system that has a single ADC module is relatively straightforward and only involves using special techniques during the design phase of the module. Once these techniques are implemented, the module can then be mass produced and the necessary precautions will come “built-in”.

Designing a DAQ system using more than a single ADC module requires some additional clocking and synchronization techniques. First of all, in order to work properly as a system, the ADCs can no longer rely on their own internal clock source. Because these clocks are all free running and are asynchronous to each other, it’s not possible for the ADCs from different modules to generate data that is digitized at exactly the same sampling rate. This, by itself, would make the operation of the DAQ system almost impossible to manage. Furthermore, any type of timing measurement between channels would be absolutely impossible to perform.

Because of this, a DAQ system having more than a single ADC module requires the use of a central clock and synchronization module. The configuration of such a module is shown in the following figure:

 Configuration of a DAQ system having more than a single ADC module with a central clock and synchronization module

A clock and synchronization module, such as Nutaq’s µSync and ADACSync clock generators, is a kind of “Swiss army knife” that provides system-wide timing functionality. A complete description of the capabilities this type of module is beyond the scope of this post, but for the present discussion, here is a summary its key features:

  • a very accurate and stable on-board reference clock that has very low phase noise characteristics
  • a GPS receiver that extracts a very accurate pulse-per-second (PPS) signal to serve as an absolute time reference from which all other generated timing signals are derived
  • an FPGA that disciplines the reference clock to the PPS signal so that it becomes accurate and stable within a few parts per billion (ppb)
  • a phase-locked loop (PLL) clock generator that uses the accuracy and stability of the reference clock to produce a wide-range variable-frequency sampling clock
  • a distribution buffer to create perfectly synchronized copies of the PLL variable sampling clock (the lengths of all traces of the multiple clock signals are carefully matched in the ADC modules)
  • configurable trigger and synchronization logic (usually internal to the FPGA) that provides system-wide synchronization signals to the ADC/FPGA acquisition modules

The following figure illustrates how the clock and synchronization module is utilized in a DAQ system that supports a large number of channels and uses multiple ADC modules:

 Clock and Synchronization module utilization in a DAQ system that supports a large number of channels and uses multiple ADC modules

In such a DAQ system configuration, all ADC modules receive exact copies of the clock and trigger signals, and operate in perfect synchronization. As before, great care must be taken to ensure that cable lengths for all signals between modules and the analog front end are properly matched.




DAQ systems monitoring more than one signal channel usually have to keep track of timing information between channels. Because of the inherent delays added to signals traveling in cables and PCB traces, it’s critical to carefully match the lengths of the signal paths to preserve the timing information between channels. In large DAQ systems, a dedicated clock and synchronization module is necessary to ensure that all modules are kept perfectly in sync. A dedicated clock and synchronization module is usually more accurate and flexible than the basic onboard resources that are included in ADC modules.