In this series:

  • How Nutaq’s Products Speed Up Your Design Flow When Using Xilinx System Generator: Part 1

Previous blog review

This is the second part of a two-part series about using Xilinx System Generator in your design workflow. Specifically, the series describes how Nutaq significantly accelerates the design process.

As I described in my previous blog post, System Generator simplifies and accelerates the development of complex DSP algorithms. Generally, the most time-consuming part is the modeling of the algorithm itself. However, considerable effort is also required to integrate your System Generator sub-module into the complete design. This is where Nutaq’s products and software tools really help you out. But, before I reveal all the secrets, some knowledge of Nutaq’s reference designs is required.

Nutaq BSDK overview

As an example, Figure 1 shows the Board Support Development Kit (BSDK) for the Perseus board. The BSDK for each solution offered by Nutaq differs slightly. Generally, the BSDK includes at one end some host PC drivers to control, monitor and exchange data with the FPGA logic. On the other end, it includes some FPGA logic (labeled Carrier FPGA in Figure 1) that can be used as a reference design. It usually contains a soft-embedded processor (MicroBlaze) for initializing and controlling the FPGA cores as well as general and utility libraries for custom applications. Extra logic is provided for the board’s input/output interfaces. For the Perseus board, this includes Ethernet, PCIe, DDR3, different FMC boards, etc. More details of the Nutaq BSDK can be found here.

The User Logic box contains the remaining FPGA logic available to the user. In our case, this is where the designer would insert his or her System Generator model. To integrate the algorithm, the designer then binds it with the different logic surrounding the User Logic box.

Figure 1 BSDK on the Perseus

Figure 1: BSDK on the Perseus

How the BSDK is reflected in System Generator

A design essentially consists of System Generator library blocks connected together in Matlab Simulink. When targeting Nutaq’s products, additional libraries are available. These libraries contain System Generator blocks that simplify bindings with the FPGA logic.

For example, the Perseus library includes:

  • Memory interfaces
  • Real Time Data Exchange (RTDex) through GE to exchange data with a remote host PC
  • Real Time Data Exchange (RTDex) through PCIE to exchange data with a remote host PC or other Perseus boards
  • Custom registers accessible from the MicroBlaze processor (and from a remote host)
  • Interfaces for specific FMC boards (MI125, MI250, ADAC250, ADC5000, Radio420X)

The designer directly replaces the model’s standard Xilinx Gateway In and Gateway Out blocks with the specific Nutaq ones. Recall our educational example presented in the first blog post, filtering samples from an ADC and forwarding the results to a remote host PC (Figure 2). In this example, we will assume that the ADC is provided by the FMC ADAC250 board and the filtered samples are transmitted to the PC through a PCIe link.

Figure 2 IO block example

Figure 2: IO block example

In addition to the ADC250 and data transfer blocks, two extra blocks are added to configure additional parameters like the clock scheme and the FIFO sizes for the data exchange with the remote PC. Their configuration menus are shown in Figure 3 and Figure 4. Figure 5 shows the configuration menu of the ADAC250 block.

Figure 3 Board configuration menu

Figure 3: Board configuration menu

Figure 4 RTDex configuration menu

Figure 4: RTDex configuration menu

Figure 5 ADAC250 configuration menu

Figure 5: ADAC250 configuration menu

The magic revealed

To recap, the methodology used to design System Generator models targeting Nutaq boards is quite similar to the usual design process. The only difference is that instead of using standard Gateway In/Out blocks, you use hardware blocks specific to the targeting board. These are packaged in a library and accessible as standard blocks. What happens then? Normally (as described in the first blog post), when the System Generator model has been completed and tested through simulation, netlist or VHDL files are generated and must be integrated within the whole design. For Nutaq’s products, this step is completely bypassed! You directly generate the FPGA bitstream. This means that after you design your System Generator model, you can perform tests directly on the hardware, thus saving a lot of time and avoiding potential errors.

Nutaq’s magic recipe contains two key elements:

  • Hardware-specific library blocks
  • Scripts called during the build process

Hardware-specific library blocks

Within each hardware block, there is eventually Xilinx Gateway In and Gateway Out blocks labeled with known names. As previously described, the Gateway In and Out blocks are used to generate the top entity of the System Generator model. These signal names within the entity are then recognized by the Nutaq’s scripts. For example, Figure 6 shows what’s hidden within the ADC250 block.

Figure 6: ADAC250 under mask

Figure 6: ADAC250 under mask

Scripts called during the build process

In Matlab Simulink, selecting the generate bitstream option under the System Generator token, calls different scripts and programs. Some are from Xilinx and part of the standard synthesis process. Others have been developed by Nutaq to perform additional work. They look at what you have instantiated within your System Generator model and then add the necessary HDL files to get the complete design and perform the binding between your model and the FPGA logic for you. Additional information can be found here.


When using System Generator as a part of a larger design, considerable effort is required to combine your System Generator sub-modules with the whole design. When targeting Nutaq’s products, this process is reduced to a single mouse click. Designers only need to use Nutaq’s hardware-specific library blocks instead of the Xilinx Gateway In and Gateway Out blocks. The Nutaq scripts take care of the rest of the work.