The MI125 FPGA mezzanine card (FMC) has analog-digital converters (ADCs) that provide 16 channels, 14-bit precision, and a sample rate of up to 125 MHz. Figure 1 shows the clock distribution circuit.

Figure 1: Clock distribution circuit diagram (from the MI125 User’s Guide)

Figure 1: Clock distribution circuit diagram (from the MI125 User’s Guide)

The MI125 ADCs are driven by clock switches which provide four options:

• 125 MHz local oscillator
• External clock front connector
• Clock from the master MI125 card (when used in double-stack 32 channels configuration)
• Clock from the carrier board

The first two options speak for themselves. The on-board 125 MHz local oscillator is included on all MI125 FMCs and can be used to synchronize the acquisition of all 16 channels on one MI125 FMC. If a different clock frequency or simply a clock source below 125 MHz is required, the front panel connector can be used to provide a custom clock to all the ADCs. In double-stack mode (in which two MI125s are connected, one on top of the other), the third option enables both cards to use the same acquisition clock through a clock switch. Finally, the last option, clock from the carrier board, needs a bit more context and explanation.

Clock from the carrier board: FPGA clock

Using an FPGA generated clock can be useful in some specific situations. The MI125 FMC does not have an internal phase-locked loop (PLL). It only has a low-jitter oscillator fixed at 125 MHz. To operate at a different frequency, its external clock connector can be used but this requires an additional hardware module. By using the FPGA clock, the internal mixed-mode clock manager (MMCM) components of the FPGA can be used to generate a wide range of frequencies. Furthermore, an external LVDS or LVCMOS clock reference can be used to generate the clock.
Driving an ADC with an FPGA clock has its drawbacks. The clock generated by an FPGA will have a lower jitter performance than a standard oscillator or analog PLL. The jitter may be few tens of picoseconds up to many hundred of picoseconds and can greatly affect the performance of the ADCs. But, driving ADC clock input from the FPGA clock can be useful due to its flexibility during the development phase of a project. For a final high-performance system, however, an external analog clock generation module is highly recommended.

Clock from the carrier board: Backplane clock

On the MI125, it's also possible to clock the ADCs with a clock provided by the carrier board directly from the uTCA backplane. The clock is routed from the carrier board to the MI125 clock switch by the FMC’s BIDIR CLK3 LVDS pins.
On the Perseus board, two clock sources can drive the FMC BIDIR CLK3 pins, as shown in Figure 2.

Figure 2: Perseus clock scheme

Figure 2: Perseus clock scheme 

There is a clock switch for selecting either the FPGA pins or a clock from the AMC backplane of the Perseus. For a clock coming from the backplane, we need to correctly set the status of the FPGA’s AU16 pin. In the default MI125 reference design, this pin is already mapped and connected to the Perseus Register core.


NET "o_CtrlAmctclkc2Fmcclk3En_p" LOC="AU16" | IOSTANDARD=LVCMOS25 | DRIVE = 2;



PORT o_CtrlAmctclkc2Fmcclk3En_p =
axiLite_perseus6010_regs_0_o_CtrlAmctclkc2Fmcclk3En_p, DIR = O

BEGIN lyt_axi_perseus6010_regs

PORT o_CtrlAmctclkc2Fmcclk3En_p = axiLite_perseus6010_regs_0_o_CtrlAmctclkc2Fmcclk3En_p

The CLK_CTRL status register section in Appendix A of the Perseus User’s Guide explains that this signal can be driven by accessing bit 10 of register 0x70000004 in the MicroBlaze processor. By default this bit is set to 0, which is the value for selecting the FPGA pins to drive the FMC BIDIR CLK3. For the clock coming from the backplane, this value needs to be set to 1.

The bitstream can be generated with the new clock configuration. Once its generation is successfully completed, the bitstream can be programmed using iMPACT.

To perform an acquisition using the newclock, modify the record command-line-interface (CLI) script.


mi125_set_clksrc 1 125mhz

mi125_set_clksrc 1 fmccarrier

This configures the clock switch on the MI125 to select the clock from the carrier board (FMC BIDIR CLK3) for operating its ADCs. To confirm that the MicroTCA backplane clock has been used as expected, a 1 MHz signal can be connected to the MI125's channel input. For example, if a provided 100 MHz clock is used, the recorded signal should have 100 samples for each period of the sinusoidal waveform.


The MI125 has many clocking options to suit your applications. The first step is to determine your required sampling frequency. Then, you define clock quality and the environment in which your system will be deployed. If you require another clock than the on-board 125 MHz, a system like the ADACSync ( would likely suit your needs if you intend to deploy your system in a lab. The ADACSync generates phase-aligned clocks to synchronize multiple systems. A signal generator could also be used. However, in the field, this additional hardware may not be accessible. In this case, having a uTCA card which would provide all the clock references needed, directly on the backplane, would enable many cards to use the same reference clock, in a more compact fashion.