In telecommunications systems, it is very important if not mandatory to maintain a stable reference time base which is shared among all elements of the system. Impairments in clocking designs, such as oscillator frequency stability as a function of temperature and load variation, induce frequency drifting which causes problems for inter-device synchronization. A relatively simple way to attain a shared stable reference time base is to use Global Positioning System (GPS) disciplined clocks.
It's sometimes overlooked that all GPS synced clocks can function as a Stratum 0 clock source for the Network Time Protocol (NTP). All GPS receivers have a Pulse-Per-Second (PPS) output that has a low-jitter and maintains absolute precision over time, as long as an adequate number of GPS satellites are available to receiver's antenna.
Typical GPS clock disciplining design
A typical GPS disciplining design includes a voltage-controlled oscillator, its associated digital-analog converter (DAC), and a digital phase lock loop (PLL). A low-cost voltage controlled oscillator is used to generate a reference frequency which is under digital PLL control. The clock disciplining logic, typically implemented within a FPGA or a CPLD device, corrects the reference frequency through the VCXO DAC.
The following diagram illustrates the flow within the design.
The clock disciplining logic uses both the disciplined clock and the system's PPS as inputs. In its simplest implementation, the disciplining algorithm counts the number of clock cycles of the disciplined clock between each PPS pulse, compares it with the actual value required by the system, and then calculates the associated error. Through a proportional-integral controller, it continuously computes a new DAC value in order to keep the frequency error as low as possible.
Clock disciplining advantages
The most obvious advantage of a GPS clock disciplining system is a very low instantaneous error in the disciplined clock. Well-designed systems and algorithms can lower the disciplined frequency stability to within 5 parts per billion (ppb), depending of the clock frequency. A low instantaneous error in sampling systems provides the following advantages:
- A very low frequency or phase drift between samples of an acquisition is expected. Temperature fluctuations of the VCXO tend to make the generated frequency drifts in one direction or the other. Otherwise, the processing on the acquired samples would have to account for this phase drift.
- For RF systems where the local oscillator clock is generated from the disciplined clock, it translates to a RF carrier frequency error.
GPS clock disciplining also allows a lower cumulative error, which is even more important than maintaining a low instantaneous error. It can constantly correct the oscillator frequency to maintain not only the exact number of clock cycles between PPS pulses, but also during the whole duration of the system's operation. A well-design disciplining system will reduce the cumulative time error to a few allowed number of samples over hours or days. To illustrate the importance of this, lets imagine a telecommunication system using time slots (such as GSM or LTE). If the clock disciplining was limited to a low instantaneous error with no concern for cumulative error, the systems sampling clock and RF carrier frequency would be very precise and at their nominal value. However, over time, this small error would add up, second by second. For example, an instantaneous error of one clock cycle per second can add up to a cumulative error of 86400 samples, which can completely desynchronize a system and make handover among systems unfeasible.
Nutaq's Radio420 and ADAC250 FGPA mezzanine cards (FMCs) natively support clock disciplining, with the help of their voltage-controlled oscillators and front-panel PPS input connectors. Nutaq also offers a GPS disciplining core for its Perseus, a Virtex-6 FPGA FMC carrier. The PPS Sync core is now available within version 6.4 of Nutaq's ADP software tools release. It is also worth pointing out that the current implementation hold-over performance is dependent on the hold-over dependence of the GPS source.