In our previous post, we briefly defined and introduced some direction finding (DF) techniques, especially the correlative interferometer method, which has a lot of advantages over the other methods. While the first post has an educational objective, this one will go deeper and discuss a possible FPGA implementation for the main processing part of the correlative interferometer algorithm. More specifically, we will:

    • review the correlative interferometer algorithm
    • present an FPGA brute force approach implementation
    • list the main hardware and software considerations
    • present a possible system configuration


Correlative Interferometer Algorithm Review

As defined in the previous post, the correlative interferometer technique consists of two main steps: the phase difference computation, and the correlation process.

1.       Phase differences computation. As illustrated in Figure 1, the phase differences between the antennas vary depending on the signal bearing. They correspond to the mismatches of the distances the transmitted signal needs to travel before reaching the co-located antennas. For this example, the antenna 1 serves as the reference channel. For a 5-channel DF antenna, five phase differences are usually sufficient.


 Phase differences for a 5-channel DF antenna

Fig. 1. Phase differences for a 5-channel DF antenna

2.       Correlation. Perform a correlation between the measured phase differences vector and a reference data set. The reference is obtained for a DF system of a known configuration at a known transmitter angle. The correlation peak indicates the best estimate for the bearing.

FPGA Brute Force Approach

The proposed implementation is illustrated in Figure 2. An FPGA uses FFT and Cordic cores to compute the phase differences. An additional configurable stage of averaging is used in order to filter the results. This brute force approach allows computing the phase differences of the complete spectrum, which means that you get a phase difference for each FFT’s bin.


FPGA uses FFT and Cordic cores to compute the phase differences

Fig. 2. Overall DF architecture

The signal amplitudes (power) might also be averaged and transmitted to the host PC. This can be useful to aggregate phase differences of successive bins belonging to the same transmitter (refer to Figure 3).


 FFT’s bin aggregation_FGPA processing

Fig. 3. FFT’s bin aggregation

In such an architecture, the FGPA performs most of the processing, while the host PC is responsible for performing the glue logic and the correlation, and displaying the results.


Hardware/Software Considerations

There are many considerations to take into account while building such a DF system. The most important can be summarized as follows:

      • Instantaneous bandwidth and frequency range. The instantaneous bandwidth and the supported frequency range greatly depend on the selected analog hardware. The antenna, the RF front-end and the ADCs fix the performance limits. Today’s antennas cover from 20 MHz to 3.6 GHz, while usual combination of front-ends and ADCs allow an instantaneous bandwidth around 100 to 200 MHz.
      • Frequency resolution. The frequency resolution is determined by the sampling frequency and the FFT size. It is obtained by the following basic formula: Sampling_Frequency / FFT_Size. The frequency resolution directly determines the amount of data there is to process, and therefore the required FPGA and host resources.
      • Integration time. The integration time is determined by the sampling frequency, the FFT size, and the number of FFTs to average. The objective of averaging is not only to smooth the computed phase differences, but also to reduce the amount of data to transmit to a host PC, thereby reducing its processing load. Unfortunately, the integration time must be smaller than the burst duration of the transmitter to get good DF results.

The following table summarizes some proposed values for two quite different transmitter types: a GSM cell phone, and a fixed FM broadcaster.

Configuration example for different transmitter types

Table 1. Configuration example for different transmitter types

Note that it’s possible to build a system that would accommodate (detect) both types of transmitters by implementing the most restrictive constraints.

FPGA Resource Usage for a System Configuration Example

This kind of proposed digital FPGA-and-host architecture can easily be mapped on a system like the Nutaq µDigitizer. Based on the μTCA architecture, this configurable system would be composed of:

      • one FMC MI250 board for data acquisition, with eight 14-bit A/D channels operating at 250 MHz (5 channels used for DF)
      • one Perseus 601X board supporting different Virtex-6 FPGA devices for the FPGA processing
      • one CPU module for host PC processing and displaying the results

The phase differences would be transferred from the FPGA to the host PC through a PCIe link.

As an example, with this hardware configuration, it would be possible to build a system with the characteristics listed in the following table:

DF system parameters
Table 2. DF system parameters

Table 3 below summarizes the FPGA resource usage for the main processing blocks of the algorithm. The Virtex-6 LX240T would be a good choice and would also leave some headroom for the extra logic required to interface and control the MI250. A bigger FPGA could also be used if more logic is required, such as implementing an energy level threshold in order to transmit to the PC only the phase differences for the FFT bins with energy.

FPGA resource estimation

Table 3. FPGA resource estimation


In this short series of two posts, we have presented a possible FPGA implementation for the main processing part of the correlative interferometer algorithm. Our approach is based on FFTs to compute the phase differences between the antennas. This technique only requires FFT and CORDIC cores, which are readily available and process the entire band at the same time.

The proposed solution naturally fits on a hardware configuration such as the Nutaq µDigitizer, composed of one FPGA board and one CPU board linked through PCIe.