In part 4 of this blog series, we will add the generated core from HDL Coder to the ZeptoSDR reference design (which is based around a Zynq processor). Let’s now open the EDK reference design. The FPGA reference design is located at the following location: C:\Nutaq\Zepto\examples_zedboard\zedboard_radio420s_bsdk. In this folder, you will find a folder named ‘bitstream’. Make a copy of this folder then rename it to bitstream_release’. Afterwards, rename the ‘bitstream’ folder to ‘bitstream_dds’. In the folder now named ‘bitstream_dds’, open the ‘zedboard-adp.ppr’ PlanAhead project file. You should see the following window:


Maximize the ‘arm_system_stub – STRUCTURE’ under ‘Design Sources’ and double-click ‘arm_system_i’. This will start Xilinx Platform Studio (XPS) and this is where we will add our pcore. After a moment, you should see the below window. Click on ‘Add/Remove IP Repositories’ on the top left:


Click on ‘Add path’ then go select the folder where your pcore folder was generated (for example, if my pcore folder is C:/work/hdl_prj, the folder to select would be C:/work/). However, for the pcore folder to be detected, you need to change the name of the folder to `pcores` (by default, the generated core will be in a folder called ipcore ex: C:/work/hdl_prj/ipcore), so you need to rename the ‘ipcore’ folder for ‘pcores’. Optionnally, you can copy the ipcore folder into the ‘pcores’ folder of the ZeptoSDR EDK reference design. Once added, our core should appear in the IP catalog tree:


Right-click on this pcore then select ‘Add IP’. A prompt box will appear asking you if you want to add one instance of this pcore in your design. Select ‘Yes’. A new window will appear:


Click ‘OK’. A second window will appear:


Select ‘User will make necessary connections and settings’ then click ‘OK’. Now, select the ‘Bus Interfaces’ tab. This will list all the pcore included in the basic ZeptoSDR reference design plus our new pcore that we just added.


As you can see on the picture above, our core needs to be connected on the S_AXI bus. By default it’s not, so you need to connect the core on the axi_interconnect_0 bus (which is the S_AXI bus on the EDK reference design). Select now the ‘Ports’ tab, next to the ‘Bus Interfaces’ tab. Find our pcore then maximize the instance to see the ports of our pcore:


These ports are linked to our Simulink model. So basically, the pcore that we created in Simulink is a blackbox with outputs created through HDL coder. We have three types of signals to connect: clock, reset and data. To send the generated DDS to the radio card of the ZeptoSDR, make sure that your connections looks like the ones in the above picture. Basically, our pcore is clocked by the data clock of the radio card. The reset signal is plugged directly to the VCC since it’s an active low signal (RESETN) and the I&Q data and I&Q select signals are plugged to the radio card DAC data port and I&Q select port, respectively. Finally, the AXI_Lite interface is clocked using the FCLK_CLK0 which is the clock for all the AXI slaves on the ZeptoSDR reference design.

Once these connections are done, you are ready to generate the netlist. This is easily done by clicking on the Hardware tab then selecting Generate Netlist. If this is not the first time that you generate a netlist for that specific project, I suggest that you do a Clean Netlist before to avoid further possible compilation errors.

Once the netlist generation is done, you can close the Xilinx Platform Studio project. We are now back to the PlanAhead project and the last step before adding Chipscope to our design is to run the synthesis. You can do this by clicking ‘Run Synthesis’ in your PlanAhead project windows.


The next step is to add Chipscope to the model before bitstream generation, to be able to validate our implementation (optional). To do this, first open the synthesized design by clicking on Synthesized Design:


The complete synthesized design will open. Now click on ‘Window’ then select ‘Chipscope’:


This will open the chipscope window. If we go back to our Simulink model, we can easily see that the signal that we want to analyze is connected to the ‘Gateway Out’ port. To find a specific net name, execute ‘Ctrl+F’ on your keyboard to open the search dialog box.


Select ‘Nets’ and ‘contains’ in the following fields.


Type ‘iq_data’ (or any other used to defined your outputs in the Simulink model) and you should the following search results:


Since our signal is actually a vector, make sure to select all twelve signals (1 for each bit) then right-click and select ‘Mark as Debug’. Repeat for others signal that you would like to debug.

Now, you just need to click the ‘Set-up Chipscope’ icon to automatically create a Chipscope core with the necessary clock. A new window will appear. Just click on next until the end.


Finally, you are ready to click ‘Generate Bitstream’. The process will generate a bitstream and a .cdc file (used with chipscope analyzer).


Once the bitstream compilation is done, you can program your FPGA with the generated bitstream (for Nutaq ZeptoSDR user, please refer to the documentation on how to make a bootable file from a generated bitstream). The last step is to open Chipscope Analyzer software and to import the generated .cdc file.



Before acquiring signals, you need to configure the radio card (remember that our core is connected to the data clock of the ADCs and DACs). To do so, you can use the provided RF calibration script which configures the radio correctly. This is located in your ZeptoSDR installation folder in Zepto\examples_zedboard\zedboard_radio420s_bsdk\remote_host\cli\launch_radio420s_rf_calibrate_demo.bat. Once the script is run, the radio is configured and our core have his clock. We can now click on the trigger button in chipscope to acquire a snapshot of the ‘iq_data’ vector and validate that our model was well implemented:


Alternatively, you can also use a spectrum scope to validate the tone generation at the output of the TX port on the front panel of the ZeptoSDR. As mentionned in the previous blogs, the frequency of the tone is linked to the clock provided to the core. By default, the RF calibration script configures the data clock of the ADC and the DAC at 76.8 MHz, which means that our core will generate a tone of 384 KHz (see part 1 for a detail explanation).