At the end of part 2, we simulated our model and created a subsytem out of our processing blocks. It is now ready for code generation. Right-click on the generated subsystem and select HDL Code->HDL Workflow advisor:


The following window will appear:


The first step (1.1) is to select ‘IP Core Generation’ as the target workflow and select the target platform. Since we simply want to generate and IP core which we will integrate in the provided ZeptoSDR reference design, selecting ‘Generic Xilinx platform’ as the ‘Target platform’ is sufficient. The third step is to select the compilation folder. A folder named ‘hdl_prj’ will be created by default at the location of your directory which contains the Simulink model by default. Click on ‘Run This Task’. The following message can appear:

Failed IP Core Generation workflow requires the starting subsystem “dds/Subsystem/Subsystem” to be an atomic subsystem. Please click the following link to turn on “Treat as atomic unit” on subsystem “dds/Subsystem/Subsystem”.

            Simply click on the hyperlink to solve this issue. Rerun this task and it should be a success. We move now to step 1.2:


This screen shows the different input/output ports of our system. As you can see on the picture above, the different ports listed are directly linked to the name of the output ports of the Subsystem. For sure, the ports could be renamed to better reflect their usage prior to HDL code generation but for the sake of our example, let’s keep it that way. The next step is to select ‘External Port’ for each of these ports since we will connect these ports to other instantiated cores later. To complete this task, click on ‘Run this task’. Go to step 2.1.

Steps 2.X are about HDL Code generation preparation. Step 2.1 checks the global settings of your environment. By checking the box ‘Ignore Warnings’, you should be able to pass this step easily:


Step 2.2 verifies for algebraic loops. There is none in our model so this step is straight forward. Step 2.3 checks for unsupported blocks in the submodel. This step should also be straight forward since we filtered the Simulink block library in part 1 of this blog series using the command ‘hdllib’. By checking the box ‘Ignore Warnings’, this test should also pass easily. The last step, 2.4, is checking for sample time errors. If you followed correctly part 2 of this blog series, there should be no problem there and everything should be ready for HDL code generation.


We are now ready for code generation. Steps 3.X should be quick. Make sure that ‘VHDL’ is selected as the selected language in 3.1.1 and keep the default configuration of 3.1.2. Once it’s done, right-click on ‘Set Code Generation Options’ then select ‘Run All’:


It should complete successfully. In the last step (3.2), we select the name and the version of the core. Default name and version is fine, just ‘Run This Task’. A ‘Code Generation Report’ will appear. In this report you can find the summary of the different sample time of the model and general information about the different ports of our core, their size but also and ‘EDK Environment Integration’ quick tutorial which proves helpful in our case:


The last blog of this blog series will be about the integration of our core in the ZeptoSDR EDK reference design. The above picture last the major steps that we will fulfill during that blog.