We have seen in previous posts that FPGA data acquisition systems, which may seem very specific in nature, can in fact be used for a wide array of applications such as:

  • Pre-clinical imaging (PET, MRI, MicroPET)
  • Radio astronomy
  • Geolocation
  • Cargo security inspection
  • MIMO radar

We also looked at the use of FPGA data acquisition systems in linear accelerators. FPGA data acquisition systems are used for two key functions within an accelerator: beam position monitoring (BPM), and low-level radio frequency (LLRF) control systems. As background, LLRF control systems manage the electromagnetic field amplitude and phase inside an accelerator. Proper electronics are essential here to ensure the highest possible beam quality. Similarly, beam position monitoring systems are essential to maintaining beam stability.

For this post, we will take a closer look at LLRF systems, and see how innovations in FPGA data acquisition systems might bring further involvement of digital electronics over analog in the years to come.


Typical Components Of A Low-Level Radio Frequency (LLRF) System


The following diagram illustrates the key components of an LLRF control system:

five key components of an LLRF control system

As we can see, an LLRF system is composed of five major elements:

  • The cavity in which the particle is accelerated
  • An analog front end to perform up/down conversion of the radio frequency (RF) signal into an intermediate frequency (IF) signal for interfacing with the FPGA data acquisition system.
  • The FPGA data acquisition system, which in a way is the ‘brain’ of the entire LLRF system. It’s a digital board featuring all the ADC and DAC required for signal conversion from the analog to the digital world, along with an FPGA processor on which the control algorithms are implemented.
  • A host PC, for communication with all the other components of the accelerator (often based on EPICS software – see here).
  • A clock generation system, to provide the various clocks required by the ADC/DAC converters and RF front-end modulators. All clocks are derived from a single reference clock to ensure proper synchronization across all the elements.

If you are new to LLRF, but familiar with system-level notions of a wireless system, you can see that the two are actually quite similar. This goes as well for the operations performed inside the FPGA, which typically include digital filtering, and ‘baseband’ IQ processing.


On The Way To A Fully Digital LLRF?


It’s interesting to note that most LLRF systems were purely analog-based not so long ago. The innovation drivers that came into play over the last years in the FPGA data acquisition system business (arrival of faster ADCs, increased processing power of Xilinx FPGAs, and arrival of FMC and AMC form factors) certainly had an impact on the way LLRF systems are now designed, supporting a transition from the analog to the digital world. Similar to what has happened with the arrival of “Zero-IF” converters for the wireless industry, new innovations are likely to push the involvement of digital electronics even closer to the cavity. Ultimately, this will allow direct sampling of the RF signals, and a simpler system architecture, as shown in the following diagram:

direct sampling of the RF signals in LLRF control system

In their paper, “Beam Position Monitor System of the ESS Linac”

[Reference: European Spallation Source], H. Hassanzadegan et al state:

”Sampling in RF has the advantage of increasing the measurement bandwidth and simplifying the design of the analogue front-end. The main drawback, is that, when implemented on an RTM, some signal degradations may occur due to the bandwidth limitation and cross talk at the connection point of the RTM to the digital module. Also, with this method, jitter requirements for the ADC clock becomes more stringent due to the higher ADC speed. Sampling in IF, on the other hand, eases the ADC sampling, because of the lower IF signal frequency and less bandwidth requirements. The compromise, however, lies in the additional complexity of the analogue front-end due to the RF-IF conversion stage.”

Therefore, there are challenges on the way. But LLRF systems, which were once purely analog, are now getting more and more digital, up to the point where analog electronics could play a very minor role.


Programming FPGA Data Acquisition Systems


A transition toward full digital LLRF means that the FPGA data acquisition system is getting somewhat of a “promotion”, requiring an ADC/DAC solution that samples even faster, and FPGAs that must perform signal processing tasks once done by the analog circuitry. Traditionally, these components would be programmed using the VHDL programming language, but now the LLRF electronics engineer may be forced to move toward higher level block-diagram programming language tools such as Xilinx® System Generator for DSP™ in order to cope with the additional complexity of these systems.

MBDK ADAC250 xilinx system generator

What is great is that FPGA data acquisition systems users would then benefit from the years of development done by software tool manufacturers. Most of this development was done to address the movement toward a full digital architecture that was driven by the wireless industry and its big push toward software defined radio (for which high-speed ADC/DAC and FPGAs were key components).


The Future Of LLRF


It’s not clear when the transition to a full digital LLRF system implementation will take place. For now, analog technology clearly has its place in reducing risk when deploying control systems in multi-million-dollar linear accelerators. Innovations such as faster ADC/DAC and more powerful FPGA devices are likely to drive FPGA data acquisition systems manufacturers like Nutaq to help achieve this transition. In the end, software tools will also be required to support engineers in charge of LLRF digital signal processing, as their responsibility in the LLRF control loop grows over time.