MIMO radar research projects have become increasingly popular over the last few years. Shedding some light on the topic, a recent article by Raytheon Co. in the Microwave Journal explained in great detail the myths surrounding the actual performance level of MIMO Radar systems, and what we should really expect from them, by underlining what they are currently good at, as well as new techniques and technologies that would be likely to support future improvements. Based in part on results obtained by MIT’s Lincoln Laboratory on their multi-function phased array radar (MPAR) system, which is an effort to develop the next generation air traffic control and national weather surveillance services, a key takeaway from the Raytheon article is that MIMO radar is ‘’best for search not for track.” The article also states that overall system size and computation components costs are currently two major roadblocks for MIMO radar deployment. This is especially true considering the trend toward “full digital” implementations, which we’ll explore in this post.
Typical MIMO Radar with Analog RF
As shown in the diagram below, past MIMO Radar projects mostly relied on analog components for phase and gain control of each antenna element. The FPGA digital electronics mainly implement control algorithms and beamforming.
Simplified FPGA-Based MIMO Radar Receiver
Such architecture was dictated mostly by the limitations (such as sampling speed and analog bandwidth of ADC converters) of the available technologies, which were for a long time not able to cope with direct RF sampling, and the overall cost of the electronics, which often relied on FPGA processors. This design has the advantage of reducing stress on the digital electronics, and also leverages existing knowledge on the analog RF side, since most of the past radar systems were based on a similar topology. In most cases, this means more stable clocking and synchronization circuitry. However, there are major cost reduction, size, and flexibility advantages which are possible when you consider offloading more processing to the FPGA-based digital beamformer system.
A First Step Toward “Full Digital” MIMO Radar Systems
Certainly, the push for MIMO architecture in the wireless industry has helped MIMO radar become viable. As FPGA processors become increasingly powerful, and ADC converters not only sample faster, but also feature four to eight times more channels than a few years ago, a movement toward full digital implementations of MIMO radar systems becomes viable not only from an R&D point of view, but even for deployment. From the perspective of an FPGA-based MIMO system provider, the most that could be done five years ago was to have 16 channels at 105 MSPS per FPGA (Xilinx® Virtex®-4 SX55 at the time). Today, it’s possible to integrate 32 channels at 125 MSPS to an FPGA that’s approximately 10 times more powerful (Xilinx Virtex-6 SX475T). Not only that, but past architectures were cPCI based, while the current ones are based on AMC and FMC form factors, which are half the size of a cPCI board. All in all, channel density by surface area has improved by a factor of 4. The image below shows a Nutaq system as an example.
From 16 to 32 Channels Per Processing Element at 1/3 the Size, Over Five Years
Since the FPGA is heart of the system, Xilinx’ continuous stream of innovation over the years in developing tools to ease FPGA design has certainly helped to address market’s need for a multichannel solution. This is not only true for MIMO radar, but is also holds for wireless (MIMO LTE), medical (PET systems), scientific (LLRF, BPM in linear accelerators), luggage/cargo scanners, and more. As an example, improvements in model-based software tools have also significantly helped designers to cope with FPGA designs that are getting increasingly complex as channels get added to the system.
Nutaq’s Model-Based Design Kit
As a result, MIMO Radar development teams now have access to FPGA-based systems that support a very high number of channels for a fraction of the cost of a few years ago. The following diagram depicts a simplified view of what a Digital IF FPGA-based MIMO radar receiver might look like now:
Digital IF FPGA-Based MIMO Radar Receiver
As stated by Yoann Paichard, RF Expert at Norwegian Defence Research Establishment, “thanks to a transition toward full digital implementation, MIMO radar analog electronics is greatly simplified and significantly increase system flexibility by having the FPGA perform not only beamforming, but also gain and phase control for each antenna element (MIMO T/R).”
Having the appropriate number of channels sampled and the required processing power to cope with the additional tasks is one consideration. From an integration perspective, FPGA MIMO radar system providers also have to consider additional system components such as clocking and control signal distribution over the entire system, SSD storage capacity, and RTOS integration.
We can see how the latest systems are addressing issues such as system costs and size, which have in the past prevented several MIMO radar projects from getting started. The viability of digital MIMO radar projects is supported not only by availability of the electronics themselves, but also by having access to mature design tools, which are sure to help developers cope with the additional complexity inherent to MIMO applications. As FPGA and ADC/DAC device technologies keep evolving, the channel density and processing power frontier is likely to be pushed to higher levels.
This will likely trigger a necessary second step: enabling multi-channel solutions to incorporate faster ADCs (250 MSPS and more) to access the entire radar bandwidth. For now, developers have access to proof-of-concept MIMO radar systems, and will mostly benefit from integrating additional features (RTOS, SSD storage, clocking systems, and so on).