Most of the software-defined radios (SDRs) currently on the market use field-programmable gate arrays (FPGAs) that offer either low power consumption or high performance. None of them really use FPGAs with the goal of accelerating the baseband host processor’s tasks. Today’s mobile communication protocols (4G and soon 5G) are highly demanding in terms of the processing power required to support real-time operations with high data rates and multi-user support.

For waveform developers who use commercial of-the-shelf (COTS) processor technology to validate and test new wireless protocols, being restricted to real-time data rates of a few mbps and a limited number of supported users can be a real challenge when designing for real-world conditions. The current GNU Radio-compatible SDRs all suffer the same pains – real-time communication bandwidth is limited to a few mbps. This limit is a result of the baseband processor struggling to perform its tasks and being limited in terms of MIPS.

Additionally, even if most of the FPGA-based SDR vendors out there claim that their systems come with a means of adding FPGA-based acceleration to boost performance, no one is making use of it; the learning curve to accomplish such tasks is quite steep for most waveform developers. Such designs require a deep knowledge of low-level hardware and software.

Most of today’s existing SDRs, like the USRP N210, propose an embedded application design within their FPGA firmware to reduce some of the baseband processor load (and thus GNU Radio load). But they are limited in the upstream and downstream path using a digital down converter/digital up converter (DDC/DUC).

This architecture helps to a certain extent but the FPGA’s maximum capabilities still aren’t used. Custom FPGA code that includes, for example, partial or overall PHY layer protocols within the FPGA fabric should drastically reduce the baseband processor load even more. But implementing this is a hard task on such SDRs. Most, if not all, lack an extensive FPGA framework to accomplish such goal or don’t have extensive reference designs to assist the developer (unlike Nutaq, which includes its QAM64 OFDM Reference Design).

Additionally, being limited to a single-dimension signal path (upstream or downstream) prevents the developer from pushing the barrier further in the acceleration of GNU Radio processes on the baseband processor.

Here is what Nutaq has done with its PicoSDR systems:

The PicoSDR simplifies user code integration in the FPGA through the use of model-based design tools and the Nutaq Model-Based Design Kit (MBDK). With Nutaq’s Real-Time Data Exchange (RTDEx) interface, multiple independent FPGA-CPU data channels can be used to create a multi-dimension signal path that accelerates GNU Radio by using FPGA fabric as a co-processor.

Nutaq’s multi-channel RTDEx simplifies the co-processing of tasks which are easily and efficiently accomplished within the FPGA (such as complex FIRs, large FFTs, CORDIC, FEC, etc). This results in a major reduction in CPU loads.

To conclude, being restricted in bandwidth or real-time operations when designing next-generation waveforms can be problematic and lead to errors in the development and validation process. The Nutaq MBDK makes it easier to target the FPGA to accelerate GNU Radio processing on the baseband processor. Even more, Nutaq’s multi-channel RTDEx IP cores provide users the right set of tools to efficiently off-load CPU processing. Finally, starting from existing, efficient reference designs like Nutaq’s QAM64 OFDM PHY layer (greater than 50 Mbps when in MIMO 2×2 mode), really accelerates the development process by letting the developer to alter the existing design to meet his or her specific needs.

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