In this series:

- From Analog to Digital – Part 1: Introduction
- From Analog to Digital – Part 2: The Conversion Process
- From Analog to Digital – Part 3: Signal Sampling
- From Analog to Digital – Part 4a: Signal Bandwidth
- From Analog to Digital – Part 4b: Signal Bandwidth
- From Analog to Digital – Part 5: Signal Conditioning
- From Analog to Digital – Part 6a: ADC Performance
- From Analog to Digital – Part 6b: ADC Performance
- From Analog to Digital – Part 6c: ADC Performance
- From Analog to Digital – Conclusion

This blog post concludes a 7-part series on the analog-to-digital conversion (ADC) process. It focuses on considerations that are outside the ADC process per se but are still important as they may be relevant to specific requirements of an ADC application.

## Better protection of the input signal

In part 5 of this series, we discussed the typical building blocks used in an analog front-end for conditioning the input signal in preparation for the analog-to-digital conversion process. We briefly mentioned the use of an output driver for the ADC as the final stage of the signal-conditioning pipeline. There are two types of output drivers that can be used to drive an ADC: single-ended drivers and differential drivers.

Single-ended drivers are amplifiers that are mainly used to provide low impedance and isolation between the analog input sensor/signal and the ADC, as shown:

Single-ended drivers are very common and are suitable for applications where the distance between the sensor/driver and the ADC is fairly short. The use of shielded cables is usually necessary to ensure that there will not be any interfering signals picked up when the signal travels between the analog front-end and the ADC.

In cases where there is a significant distance between the analog front-end and the ADC, the driver’s low impedance and the cable’s shielding might not be sufficient to provide adequate protection from interfering signals. In these cases, the use of balanced (or differential) drivers and receivers should be considered.

A differential driver is a special type of amplifier that has two outputs: an amplified copy of the input signal and an amplified and inverted (180° out-of-phase) copy of the input signal.

When written as an equation (with the gain of the driver set to unity), we get:

*A=+Input *

*B= -Input*

The differential driver is paired with a differential receiver that creates a single-ended signal by subtracting the two analog signals present at its inputs.

When written as an equation (with the gain of the receiver set to unity), we get:

*Output= A-B*

The main advantage of using differential drivers and receivers is demonstrated in the following figure:

In this example, a very long cable is used to connect the analog front-end and the ADC. The cable picks up some induced interference along the way, as represented by the purple spike. Because the interference is most likely induced simultaneously in both conductors inside the cable (they are very close and are usually wrapped around each other), it is referred to as being induced in *common-mode*. The resulting modified signals are shown at the output of the cable. Using the previously shown equations, the signal at the input of the cable consists of:

*A=+Input*

*B= -Input*

But the signals at the output of the cable have been altered to become:

*A=+Input+noise*

*B= -Input+noise*

The signal at the output of the differential receiver is:

*Output=(+Input+noise)-(-Input+noise)*

*Output= +Input+noise+Input-noise*

*Output= +2 Input*

As we can observe, the differential receiver eliminates the common-mode components induced in the cable and generates an unaltered copy of the original input signal. The use of differential (or balanced) drivers and receivers is a simple technique to provide good signal immunity when the sensor is remotely located from the ADC.

## Better clocking signal

The quality of clock signals used in digital electronics is usually very good and is often taken for granted. While their quality might be adequate for digital electronics in general, things are completely different when having to work with high-speed, high-resolution ADCs.

Manufacturers of ADC modules (like Nutaq) usually provide on-board sampling clock sources that guarantee the best possible conversion performance from the ADCs present on the module. Most modules also have provision for an external clock source so that the user can adapt the module’s sampling rate for one that is best suited for a given application. Providing a dedicated sampling source requires some additional considerations and precautions.

The most important factor to take into consideration for an ADC clock source (both on-board and external) is its *phase noise.* Phase noise is a measure of the uncertainty in time for the rising edge of the clock signal from one cycle to the next. The phase noise is usually qualified as a function of the spectral density of the clock signal’s inherent noise in the frequency domain, for which a corresponding uncertainty in the time domain, called *jitter*, can be computed. The relationship between the frequency and time domain representations of phase noise can be complex (it will probably be the subject of a blog post in the near future). For the time being, we will concentrate on the time domain representation and its impact on ADC performance.

The following figure illustrates how the jitter on the rising edge of the clock signal creates uncertainty on when/where the input signal is sampled by the ADC.

We can easily observe that an error in the location of the rising clock edge directly translates to an error in the sampled value for the input signal (∆S_{rms} is proportional to ∆t_{rms}). We can also conclude from the above figure that ∆S will be proportional to the slope of the signal, which increases according to the frequency of that signal.

Another way to look at the incorrectly acquired samples would be to consider that we are using an ideal clock that does not have any inherent phase noise, and that it is instead the signal itself that fluctuates back and forth in a random manner. In doing so, we transform the jitter of the clock into an equivalent form of frequency modulation (FM) of the input signal. This is validated when we look at the digitized signal in the frequency domain.

The phase noise creates modulation sidebands on each side of the carrier frequency in the frequency domain. The exact shape of the “skirt” surrounding the carrier depends on the spectral density and distribution of the clock’s phase noise. The random fluctuations of the signal correspond to a form of “blur” in the time domain that is interpreted as an uncertainty of the exact frequency of the signal in the frequency domain. Observing a “skirt” surrounding a signal in the frequency domain is a very common way of detecting problems with the phase noise of ADC’s sampling clock.

Going back to the error caused by the clock jitter when sampling a sine wave signal, we can compute the worst-case value for ∆S, which occurs at the mid-point of the wave (also called the *zero-crossing*).

*slope= ∆S/∆t= 2πf (for very small ∆t at zero crossing)*

*∆S=2πf∆t*

It is easy to observe in the above figure that the analog signal’s sampling error caused by the sampling clock jitter is very similar to the error caused by the ADC quantizer. In part 6a of this series, we determined that the signal-to-noise ratio of an ADC due to the quantizer noise was given by the following equation:

Assuming a sine wave signal with an amplitude of 1 unit_{rms}, the SNR of the ADC resulting from the clock jitter (equivalent to ∆t_{rms}) is:

Since the ADC’s SNR is the result of a combination of both the signal’s frequency and the jitter of the sampling clock, it can be represented by a family of curves as shown below.

In part 6c of this series, we determined that the effective number of bits (ENOB) of an ADC was related to the SNR by the following equation:

The ENOB corresponding to the SNR is shown in the right side of the above figure. For example, a 14-bit ADC will only have a resolution equivalent to 12 bits if it digitizes a 100 MHz signal with a clock jitter as high as 250 fsec_{rms}.

## Conclusion

In this last part of our series on the analog-to-digital conversion process, we discussed two different ways of optimizing the performance of an ADC. The first method proposed a way to protect the integrity of an analog signal travelling over long distances by using differential drivers and receivers at both ends of the cable connecting the source signal to the ADC. The second method described the impact of a sampling clock phase noise on the performance of an ADC and how to compute the maximum acceptable jitter in relation to the frequency of the digitized signal.

We hope you enjoyed this series on ADC performance and that you learned a few interesting things along the way!