RF Specification |
|
Receiver |
|
|---|---|
| RF Input | MMCX (50 Ω)
2×2 : 2 Channels 2×2-E (With CPU) : 2 Channels 4×4 : 4 Channels |
| Architecture | Zero-IF (direct conversion) |
| Tuning range | 300 MHz to 3800 MHz |
| Frequency resolution | 2.4 Hz |
| PLL settling time | 20μs + FPGA Programmation (I2C) |
| Pre-select RF filter bank | 14x Selectable RF band pass filters or Bypass mode |
| Baseband configurable low-pass filter | 0.75 MHz to 14 MHz (RF channel bandwidths from 1.5 MHz to 28 MHz) |
| Typical noise figure | 10 dB |
| IMD3 | Low band: -61 dBc to -56 dBc
High band: -50 dBc to -45 dBc |
| Wideband noise floor | -100 dBFS |
| Sensitivity (SNR=5 dB and bandwidth=200 kHz) | Low band: -103 dBm
High band: -90 dBm |
| Gain control range | Low band: 79 dB
High band: 73 dB |
| Absolute maximum input power | -13 dBm |
| I/Q balancing | Auto-Calibrated (Software Provided) |
| SFDR | 50 dBc |
Transmitter |
|
| RF Output | MMCX (50 Ω)
2×2 : 2 Channels 2×2-E (With CPU) : 2 Channels 4×4 : 4 Channels |
| Architecture | Zero-IF (direct conversion) |
| Tuning range | 300 MHz to 3800 MHz |
| Frequency resolution | 2.4 Hz |
| PLL settling time | 20μs + FPGA Programmation (I2C) |
| Baseband configurable low-pass filter | 0.75 MHz to 14 MHz (RF channel bandwidths from 1.5 MHz to 28 MHz) |
| Output: IMD3 | -60 dBc |
| Wideband noise floor | -124 dBc/Hz |
| Spur | Inband: -100 dBc
Adjacent channel: -60 dBc |
| Total gain control | 70 dB |
| P1 db output | Low band: 10 dBm (typical)
High band: 5 dBm (typical |
| Typical carrier suppression | -50 dBc |
| Sideband suppression | -45 dBc |
Digital Specification |
|
| CPU | Option: Intel Quad-core i7 Gen2 CPU, 2.1 GHz processor) |
| FPGA | Option 0: Xilinx® Virtex®-6 LX240T Option 1: Xilinx® Virtex®-6 LX550T Option 2: Xilinx® Virtex®-6 SX315T |
| Non-volatile memory | 64 MB (FPGA)
64 GB + SATA expansions (CPU) |
| RAM | 4 GB DDR3 (FPGA)
18 MB QDR2 (FPGA) 128 MB DDR3 (FPGA) 8 GB DDR3 (CPU) |
| Operating System | Linux (Ubuntu/Debian/Fedora)
Windows (Win7) |
| System Interface | GigE, PCIe, USB Consol, JTAG, USB (CPU Option), SATA (CPU Option), HDMI (CPU Option) |
| Radio (FPGA-CPU) Data Link | GigE (900 Mbps sustained throughput)
PCIe 4x (6.4 Gbps sustained throughput) |
| Typical Power Consumption | 2×2 : 35 W (Min : 3 W)
2×2-E (With CPU) : 55 W (Min : 3 W) 4×4 : 70 W (Min : 3 W) |
System Reference Clock Specification |
|
| Type | Voltage Controlled Crystal Oscillator (TCVCXO) |
| Frequency | 30.72 MHz |
| Frequency Accuracy | 2 ppm |
| Frequency Warping | using on-board D/A converter (16-bit) |
| GPS-Disciplined | Using an external PPS Input (FPGA control) MMCX |
| Alternate Clock Input Option | External clock/reference input on MMCX |
| Clock Output | User selected Clock on MMCX, used for multi radio-head daisy-chain synchronisation |
Power Supply |
|
| PicoSDR supply input | 12 VDC |
| Provided External PSU | Universal 100-240 VAC |
Physical Specification |
|
| Dimensions | h: 48 mm, w: 215 mm, d: 290 mm |
| Weight | 2×2 : 2.4 Kg
2×2-E : 2.6 Kg 4×4 : 2.4 Kg |