In this series:
- How to implement a Rayleigh fading channel in FPGA – Part 1: Generation of correlated Rayleigh random variables
- How to implement a Rayleigh fading channel in FPGA – Part 2: The hardware architecture of a Gaussian random variables generator
- How to implement a Rayleigh fading channel in FPGA – Part 3: The hardware architecture of a Rayleigh random variables generator
- How to implement a Rayleigh fading channel in FPGA – Part 4: A model-based implementation of a Rayleigh random variable generator
In Part 4 of this blog series, we implemented and simulated a correlated Rayleigh random variables generator model with aid of Xilinx’s System Generator toolbox in the Simulink environment
Figure 1: Targeting the correlated Rayleigh random variable generator for the Perseus platform
In Figure 1, we need to enable the input and output ports of this design to exchange data with the real world. The custom registers (CR) on the Perseus are the simplest way to modify the design's input parameters via Nutaq’s command line interface (CLI) software. The Record block is used to put the correlated Rayleigh random variables into the 1 GByte of on-board SDRAM. The MemToHost block works in conjunction with the RTDEx block to send the results from the SDRAM to the host. A ChipScope block connects to the output ports for observing the generated signals.
The Perseus 601x block configures the design clock source at 100 MHz. The RTDEx configure block configures the RTDEx core operation (in this example, the Gigabit Ethernet interface is used for data exchange). Finally, the System Generator block is used to generate the design’s bitstream.
Interacting with the design
Real-time monitoring of the real and imaginary components of the correlated Rayleigh random variables generator can be performed via the ChipScope block, as shown Figure 2. ChipScope is well-suited for debugging purposes since its capture depth depends on the availability of block RAMs inside the FPGA. Therefore, a combination of Record and RTDEx features is an efficient approach for capturing a large amount of data. The recording depth depends on the maximum capacity of the on-board SDRAM on the Perseus platform.
Figure 2: ChipScope of the correlated Rayleigh random variables generator output
The following CLI code snippet is used to record 4 Mbytes of results (equivalent to 220 complex samples) via the Record and RTDEx interfaces.
shell echo Connecting to Perseus... connect 192.168.0.109 shell echo Initializing SDRAM... ram_init shell echo Recording results... recplay_record 4194304 recplay_record_check_transfer_done 100 shell echo Transfering to host... ram_get ../fpga/record_data.bin 0 4194304 1024 50000 shell echo Done!
The resulting amplitude and phase of 1000 hardware-generated correlated Rayleigh samples and the probability density function (PDF) over 220 samples obtained from Record and RTDEx are shown in Figure 3 and Figure 4, respectively.
Figure 3: Magnitude and phase of the correlated Rayleigh generator output
Figure 4: PDF of generated correlated Rayleigh random variable versus theoretical Rayleigh PDF
You can see that the hardware-generated random variable PDF closely follows the theoretical Rayleigh PDF as expected.
Conclusion
This blog post showed a simple, fast, and efficient model-based implementation of a Rayleigh random variable generator example on the Virtex-6 FPGA used by Nutaq’s Perseus development platform [1]. The implementation is now ready for use as a baseband flat-fading or multipath Rayleigh fading channels emulator.
References
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[1] |
M.-Q. Nguyen. How to implement a Rayleigh fading channel in an FPGA – Part 4: A model-based implementation of a Rayleigh random variable generator. [Online]. http://nutaq.com/blog/how-implement-rayleigh-fading-channel-fpga-%E2%80%93-part-4-model-based-implementation-rayleigh-random |
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[2] |
Nutaq Inc. Nutaq Perseus 601X. [Online]. http://nutaq.com/products/perseus-601x |