In this series:

- How to implement a Rayleigh fading channel in an FPGA – Part 1: Generation of correlated Rayleigh random variables
- How to implement a Rayleigh fading channel in an FPGA – Part 2: The hardware architecture of a Gaussian random variables generator
- How to implement a Rayleigh fading channel in an FPGA – Part 3: The hardware architecture of a Rayleigh random variables generator
- How to implement a Rayleigh fading channel in an FPGA – Part 5: Targeting a Rayleigh random variables generator for Nutaq’s Perseus 601x platform

In Part 4 of this series, I explain how to design the correlated Rayleigh random variables generator using Xilinx’s System Generator model-based workflow. First, let’s look at the implementation of the correlated Rayleigh random variables generator from the inside out. Figure 1 shows the overall hardware architecture of the correlated Rayleigh random variables generator, as discussed in part 3 of this blog series

**Figure 1: Architecture of a Rayleigh random variable generator**

## Uniform and Gaussian random variables generator

**Figure 2: Model-based implementation of Gaussian random variables generator**

The starting point for the implementation of a Rayleigh random variable generator is to implement a Gaussian random variables generator, as mentioned in Part 2 of this series [2]. The Tausworthe algorithm is used to implement a 32-bit uniform number generator. It provides fast, superior randomness that occupies less area in the field-programmable gate array (FPGA). The initial seed values of this uniform random generator are randomly chosen. The F_ROM and G_ROM blocks contain quantized approximations of the f and g functions mentioned in [3]. They are addressed by the output of the uniform random generator blocks. The MULT block is a pipeline real multiplier with full-scale output. Input to the accumulator is truncated before performing accumulation to realize the central limit theorem in order to overcome quantization and approximation errors. As a result, the Gaussian generator generates one sample every four clock cycles (the accumulator accumulates four samples before generating the Gaussian distributed random variable). Simulation results can be validated by an output scope or a variable dump to a MATLAB workspace.

## Rayleigh random variables generator

Putting it all together, Figure 3 shows a model-based implementation of the correlated Rayleigh random variables generator. The Gaussian random generator (magenta block) generates two independent real and imaginary rails. The configurable fast Fourier transform (FFT) processor (orange block) is configured to 1024-point complex inverse FFT (IFFT). IFFT stage schedule scaling, and continuous streaming mode are configurable via user ports. It is worth noting that the IFFT length must be configured before starting the IFFT processing. The normalized Doppler shift of 0.05 is preloaded into the Doppler filter (green block). Filtered complex Gaussian distributed random variables in the frequency-domain are then injected into the IFFT processor to generate the time-domain Rayleigh distributed random variables.

At this point, the Rayleigh random variables generator block is ready for simulation. A few scopes and variable dumps to MATLAB workspaces are used to validate the implementation. For example, the magnitude and phase simulation results captured from the Rayleigh random variables generator model are shown in Figure 4.

**Figure 3: Model-based implementation of the Rayleigh random variables generator**

**Figure 4: Rayleigh random variables generator simulation results**

## Conclusion

This blog post showed a model-based implementation of the Rayleigh random variable generator that is simple, fast, and efficient. In upcoming blog post, we will use Nutaq’s Perseus 601X development platform to test this implementation on a Virtex-6 FPGA [4].

## References

[1] |
M.-Q. Nguyen. How to implement a Rayleigh fading channel in an FPGA – Part 3: The hardware architecture of a Rayleigh random variable generator. [Online]. http://nutaq.com/blog/how-implement-rayleigh-fading-channel-fpga-%E2%80%93-part-3-hardware-architecture-rayleigh-random |

[2] |
M.-Q. Nguyen. How to implement a Rayleigh fading channel in FPGA – Part 2: The hardware architecture of a Gaussian random variable generator. [Online]. http://nutaq.com/blog/how-implement-rayleigh-fading-channel-fpga-%E2%80%93-part-2-hardware-architecture-gaussian-random |

[3] |
R. C. Tausworthe, "Random number generated by Linear Recurrent Modulo Two," |

[4] |
Nutaq Inc. Nutaq Perseus 601X. [Online]. http://nutaq.com/products/perseus-601x |