PicoDigitizer 125-Series


PicoDigitizer 125-Series

High processing power, high channel density, and a low system cost-per-channel.

An FPGA-based table top DAQ solution incorporating up to 32 channels at 125 MSPS on a Virtex-6 FPGA.

  • 16 or 32 channels at 125 MSPS
  • High channel density yields low system cost
  • Large Virtex-6 FPGA
  • Model-based design integration
  • Phase aligned channels, phase coherent sampling
  • Embedded version available
  • GigE and PCIe 4x

The PicoDigitizer 125-Series presents developers with a large Virtex-6 FPGA which can optionally be used in conjunction with an embedded Quad Core i7.

16 or 32 phase coherent channels of high speed data, sampled at 125 MSPS with 14 bit resolution, are captured and processed in this small table top platform...yielding a solution that offers high processing power, high channel density, and a low system cost-per-channel.

To reduce overall system development time, designers can choose to use a model-based design approach (via Simulink) which enables real-time and hardware-in-the-loop co-simulation with the FPGA. Alternatively, a VHDL-based FPGA framework is also available.

Built for intensive processing requirements...with optional FPGA-CPU mixed architecture

The large onboard Virtex-6 FPGA of the PicoDigitizer 125-Series can be used for demanding processing requirements such as:

  • Digital-pulse-processing
  • Up-conversion, down-conversion
  • Space-time coding
  • Beamforming

For those looking to balance power, speed, and performance, a Quad Core i7 can be embedded into the PicoDigitizer 125-Series.

Shortened development time with fewer hardware cycles

A model-based design environment (MATLAB Simulink & Xilinx System Generator) means rapid transitions from algorithm design to hardware-in-the-loop testing. The net result is a development cycle that can be reduced by weeks or months.

Add to this the ability to automatically generate HDL code from the development environment and you have another significant source of reducing the time taken to develop your scientific or medical imaging applications.

Includes Recording IP core

Data exchange with the embedded or external CPU is enabled via either a GigE or PCIe interface, while data can be recorded using Nutaq’s multichannel Record & Playback IP core.

Begin your "value add" development right away

The PicoDigitizer 125-Series ships with a software suite that contains all of the necessary IP cores, IO interfaces, and stand alone APIs need to enable immediate development of applications on the hardware.

High channel density means lower system costs...and a small footprint

Select either 16 or 32 phase coherent channels sampling at 125 MSPS. Our double-stack FMC technology not only saves you money, but also allows for a reduced footprint in our table top digitizer solution.

FPGA Supports LX240T, LX550T, SX315T and SX475T FPGA devices 
  Supports up to 2 PCIe (4x) interfaces; Supports GigE interface
  64MB NOR Flash
  128 MB DDR3 SRAM Dedicated for Nutaq CCE (Central Communication Engine application) and Microblaze Embedded Linux OS
  Includes a complete framework for Virtex-6 interfaces (Nutaq BSDK)
Embedded CPU Section CPU: Intel Quad-core i7 Gen2 CPU, 2.1 GHz processor
  64GB SSD
  GigE & Dual PCIe 4x support
  SATA –II/III support
Sampler Coupling AC or DC coupled ordering option
  Single-Ended or Differential inputs ordering option
Sample Characteristics 14 bit
  125 MSPS maximum
  16 or 32 channels
Sampling Clock Onboard crystal 125 MHz, 2 fsec RMS jitter
  External sampling CLK input
Performance Analog input Bandwidth : 80 MHz (-3dB)
  SNR (dB): 67 (@ 1 MHz) , 66 (@ 30 MHz), 64 (@ 70 MHz)
  SFDR (dBc): 70 (@ 1 MHz) , 75 (@ 30 MHz), 75-AC / 72-DC (@ 70 MHz)
  THD (dBc): 69 (@ 1 MHz) , 83 (@ 30 MHz), 80-AC / 73-DC (@ 70 MHz)
  Worst inter-channel Crosstalk (dBFS): 58-SE / 75-Diff (@ 30 MHz) 
  *AC = AC Coupled, DC = DC Coupled, SE = Single-Ended, Diff = Differential


Interactive Channelizer Demonstration
Posted on Title
2014-07-07 Release 6.5 is coming soon! – Part 3: Ubuntu and Debian support
2014-06-27 How to play MUSIC with a PicoDigitizer: Part 1
2014-05-21 RTDEx Gigabit Ethernet: Reliable data retrieval from DDR3 memory
2014-05-12 Release 6.5 is coming soon! - Part 1
2014-02-28 Passive Bistatic Radar Systems
2014-01-06 PET scanners with rapid data acquisition (DAQ) hardware
2014-01-02 Radar
2013-09-26 Massive MIMO technology: The big shift for next generation wireless broadband communications
2013-09-16 A success story: Using FPGA technology for radio astronomy
2013-08-29 From Analog to Digital – Part 7: Precautions
2013-08-26 The Record and Playback Module Part 3: Playback mode
2013-08-19 The Record and Playback Module Part 2: Implementation and Record Mode
2013-08-13 The Record and Playback Module
2013-08-07 Passive Radars - Enabling Technologies Making It A Growth Industry
2013-08-06 Design Workflow of an FPGA-based Digital Control System
2013-08-02 How Nutaq’s products speed up your design flow when using Xilinx System Generator: Part 2
2013-07-11 How Nutaq’s Products Speed Up Your Design Flow When Using Xilinx System Generator: Part 1
2013-07-04 Controlling The MRI Using FPGA Based Digital Spectrometers
2013-06-19 Data Communication in Nutaq MicroTCA Systems
2013-06-17 Incremental Innovation : Why we need Particle Accelerators
2013-06-12 Using FPGAs For Digital Pulse Processing In Spectrometer Systems
2013-06-10 From Analog to Digital – Part 5: Signal Conditioning
2013-06-04 A Study of Pulse Characteristics in Active Radar
2013-05-31 MIMO Radar and Phased-Array Radar
2013-05-30 Data Communication in MIMO Radar Systems
2013-05-22 From Analog to Digital – Part 4b: Signal Bandwidth
2013-05-17 Active vs. Passive Radar
2013-05-16 An FPGA Implementation Feasibility Study of the Correlative Interferometer Direction Finding Algorithm - Part 2: In Depth
2013-05-10 Advantages of an AMC Approach for MIMO Radar Systems
2013-05-08 From Analog to Digital – Part 3: Signal Sampling
2013-05-03 An FPGA Implementation Feasibility Study of the Correlative Interferometer Direction Finding Algorithm - Part 1: Algorithm Review
2013-05-02 Using Nutaq’s CLI and IEEE POSIX Pipes as an Alternative Interface to µDigitizer
2013-05-01 From Analog to Digital – Part 2: The Conversion Process
2013-04-30 Digital Implementation of MIMO Radar Systems
2013-04-29 Controlling the Processing and Acquisition Sub-System in a Data Acquisition System
2013-04-25 Simulink, System Generator, and Nutaq’s MBDK: The Toolkit for FPGA-based DAQ Systems Development
2013-04-22 Accelerating FPGA-based Multichannel Pulse Processing With Recorded Test Vectors and a Model-Based Design Approach
2013-04-18 Multi-Channel Synchronization In FPGA-Based DAQ Systems
2013-04-11 Using FPGAs in High Channel Count Data Acquisition Systems
2013-04-10 Data Acquisition Systems Overview
2013-04-09 Selecting The Best I/O Board For Your Application
2013-04-05 Nutaq’s Data Recording Solutions For FPGA-Based Data Acquisition Systems
2013-04-04 PET/MicroPET Conventional Design, Limitations and Improvements (Part 2): Improving Design Using ADC, FPGA and DSP
2013-04-03 FPGA Implementation Of A Digital Pulse Processing Algorithm For Baggage And Cargo Scanning
2013-03-28 Controlling The Front-End Of An FPGA Based Data Acquisition System
2013-03-27 Front-End Electronics: Nutaq’s Role In Reducing Micro-PET And PET System Costs
2013-03-25 Digital LLRF: What Will Future FPGA Data Acquisition Systems Look Like?
2013-03-20 PET/MicroPET Conventional Design, Limitations and Improvements (Part 1)
2013-03-19 Using a Model-Based Approach to Ease the Implementations of FPGA Data Acquisition Systems
2013-03-18 The Advantages of Using FPGAs in High Speed, High Density Data Acquisition Systems
2013-03-08 Cost Effective Multichannel Data Acquisition With FPGAs
2013-03-07 Optimizing the Number of Analog-To-Digital Converters in Small Animal Imaging (SAI) Systems
2013-03-05 Radioisotopes and Their Impact on Preclinical Imaging ROI
2013-02-26 Small Animal Imaging Systems : Addressing The Costs

Up to 32 Channels, 125 MSPS A/D FMC

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