ADAC250

Name

ADAC250

Designed for high speed, synchronized, phase-coherent multichannel applications.

The ADAC250 FMC integrates a dual 14-bit, 250 MSPS A/D converter with a dual 16-bit, 1 GSPS D/A converter. Supports multiple clock and synchronization modes in an industry standard VITA 57.1 form factor.

  • 2x 14 bit, 250 MSPS ADC
  • 2x 16-bit, 1 GSPS DAC
  • Programmable gains on both converters
  • Xilinx ML605 Reference Design
  • Wideband, AC-coupled I/Os
  • 2–4x interpolation modes on DAC
  • Low-jitter reference clock and synchronization PLL
  • Supports external triggers

Features that make ADAC250 unique

Flexible Clock Management

Industry Standard Mezzanine Card

Use A GPS Disciplined Clock

Offers low phase noise clock distribution, a bypassable PLL core, bypassable dividers, and the possibility to adjust the phase of five clock outputs.
Uses the VITA 57.1 standard, making it easy for developers to integrate FPGAs into their embedded system designs.
A PPS signal can be sent to the carrier’s FPGA to dynamically adjust the ADAC250’s onboard VCXO through its SPI DAC.
     

 

ADAC250 Block Diagram
ADAC250 Clock Management Block Diagram
Posted on Title
2014-08-26 Using FPGAs In Multichannel DAQ Systems
2014-08-06 Implementation of Gardner symbol timing recovery in System Generator
2014-07-22 Phase Lock Loops: Part 1
2014-07-21 Bit error rate measurement in a simple BPSK communication chain
2014-06-17 Digital I/Q demodulator with a high-speed ADC
2014-06-10 All you need to know about Nutaq's team - Dr. Minh-Quang Nguyen, GSM/Network Sortware Designer
2014-06-06 Multiplier-less IF mixer for digital up converter
2014-05-13 All you need to know about our technical leaders - David Quinn, FPGA technical leader
2014-05-09 Xilinx System Generator tips and tricks – Part 3: Using MATLAB M-function for easy state machine coding
2014-04-25 Xilinx System Generator tips and tricks – Part 2: HDL code reusability
2014-04-10 All you need to know about our technical leaders - Dr. Messaoud Ahmed-Ouameur
2014-03-14 Nutaq FMC compatibility chart
2013-11-15 GPS disciplining of an RF system clock
2013-10-25 A Step by Step ADC/DAC Tutorial Series Part 5
2013-09-10 From Analog to Digital – Conclusion
2013-09-03 A Step by Step ADC/DAC Tutorial Series Part 3: Software installation validation and the first steps with MBDK
2013-08-29 From Analog to Digital – Part 7: Precautions
2013-08-26 The Record and Playback Module Part 3: Playback mode
2013-08-13 The Record and Playback Module
2013-08-06 Design Workflow of an FPGA-based Digital Control System
2013-08-01 A Step by Step ADC/DAC Tutorial Series Part 2: Overview of the ADAC250 FMC and the installation of the development software
2013-07-29 From Analog to Digital – Part 6c: ADC Performance
2013-07-17 Wideband SIGINT Application: Spread-Spectrum Technology
2013-06-10 From Analog to Digital – Part 5: Signal Conditioning
2013-06-04 A Study of Pulse Characteristics in Active Radar
2013-05-29 A Step by Step ADC/DAC Tutorial Series Part 1: Introduction
2013-05-22 From Analog to Digital – Part 4b: Signal Bandwidth
2013-05-08 From Analog to Digital – Part 3: Signal Sampling
2013-04-30 Digital Implementation of MIMO Radar Systems
2013-04-24 From Analog to Digital – Part 1: Introduction
2013-04-09 Selecting The Best I/O Board For Your Application
2013-03-18 The Advantages of Using FPGAs in High Speed, High Density Data Acquisition Systems
Perseus 601X

Virtex-6 AMC with HPC FMC site

PicoDigitizer 250-Series

High speed, FPGA based ADC-DAC processor.

µDigitizer

Flexible μTCA architecture allows for optimal number of conversion channels, FPGA processors and storage units to match application needs.

LinkedIn Twitter YouTube Vimeo