Beyond the ability to simulate, all designer engineers will one day face the need to debug a design in the physical hardware world. With Nutaq’s MBDK FPGA environment, this is easily done with any of the following methods:
• Using the Xilinx System Generator ChipScope block
• Using Nutaq’s RTDEx MBDK block for direct data exchange between a host PC and the hardware
• Using Nutaq’s RTDEx together with Nutaq’s Record-Playback MBDK blocks
In the first part of this blog, we are going to show how easily debugging an FPGA design can be with the Xilinx System Generator ChipScope block. In the second part, we’ll show how it’s even more convenient to use Nutaq’s RTDEx and Record-Playback MBDK blocks.
Part-1: Step-by-step debugging your FPGA MBDK design with the Xilinx System Generator ChipScope block.
In Nutaq’s MBDK environment, ChipScope is provided by the Xilinx System Generator library in the form of an easy-to-use block. Under System Generator, all blocks run at the design’s master clock. Probing low frequency signals can be a tricky business when the ChipScope clock is much higher (for example, your design runs at 80 MHz and you want to probe a sinus at 1 MHz). In this case, you will barely be able to see a few points of your sinus over a 1024 sample deep capture buffer.
In this post, we describe the steps you can follow to use the ChipScope block to debug your FPGA MBDK design and to be able to display a few periods of your low frequency signals. We chose the Nutaq GNU Radio420 as an example so we can probe the signal in three different stages of its signal processing. This shows how to scope a signal at different rates and frequencies in the same design.
1. In the Simulink Library Browser, select the Xilinx Blockset library and click Tools. Then, drag a ChipScope block into your design.
2. In your design, double-click on the ChipScope block to open its configuration dialog box. Configure it to use 3 triggers ports and 3 data ports. Also, change the Match type to “Basic with edges” for each port and change the depth of the capture buffer to at least 1024 samples.
3. Connect the signals to probe to the data ports of the ChipScope and connect their corresponding valid strobe to the corresponding trigger ports (trig) of the ChipScope.
If the signal you want to probe does not have a valid strobe, use the Xilinx Clock Probe block as shown in the figure below. This extracts the signal rate so you can trigger ChipScope capture on it.
4. Click on the signals connection to name them. This will allow signal identification in the ChipScope analyzer window later on. Click CTRL-D to refresh your model and to see the ChipScope ports name change. Save your model and compile it as usual. Once done, load your bitstream to the platform.
5. Connect your Xilinx JTAG to the platform and to your computer and then open the ChipScope analyzer tool from Xilinx software suite. From the Analyzer menu, click the Chain square (top-left corner) to connect to the platform’s FPGA JTAG chain.
6. You should see the ChipScope showing an integrated logic analyser (ILA) unit. Currently, the signal names are generic and it’s hard to follow which one is which. From the File menu, click Import. Browse for the CDC file that was automatically created by the system generator (it’s located in your working directory, the directory you specified as the target directory in the system generator token). This will put correct naming on the signals and even automatically group them into buses.
7. By default, the Trigger Setup and Waveform windows are open. In the Waveform window, right-click on each signal bus and change its radix to Signed Decimal. You may also change the waveform color to distinguish different signals.
8. In the Trigger Setup window, change the triggers values from X to 1 and change the Type to N Samples so we capture only valid signal samples. This allows us to display at least a couple of periods of the captured signal. You can only use one trigger signal at a time or a combination of all trigger signals. Hence, you will need to switch to a corresponding trigger port each time you want to capture a different signal.
9. In the Project tree (top-left), select Bus Plot to open a window. Select the signals you want to display and click the Play button (top menu). This will capture and display a buffer of 1024 valid samples of the selected signal, regardless of your design master clock rate.
10. You can export your capture buffer for offline analysis by using Nutaq’s Matlab scripts or any other script for data parsing and alalysis. From the File menu, click Export and choose what to export and select the file type and location.
We showed how easy it is to debug your MBDK FPGA design in hardware by using the Xilinx System Generator ChipScope block. You can use it to probe a chip signal in your design at different stages of its processing. ChipScope’s
only disadvantage is that the FPGA resources needed to implement it increase as you increase capture buffer depth (especially the RAMB memory blocks of the FPGA). This can lead to timing problems in your design. Also, to debug with ChipScope, you need a JTAG hardware probe.
In the next part of this post, we will show how to use Nuaq’s RTDEx and Record-Playback blocks to increase capture buffer depth without requiring extra FPGA resources or having to recompile your model each time you need to change the capture buffer depth.