The Radio420X FPGA mezzanine card (FMC) functions as the RF interface for Nutaq’s ZeptoSDR, PicoSDR, and TitanMIMO-4 systems. It is based on the LMS6002D direct-conversion RF integrated circuit (RFIC) from Lime Microsystems. In this two-part series, we look at how the Radio420X performs in a frequency-hopping spread spectrum (FHSS) context. More precisely, we study the blanking internal, the time during a hop when data cannot be received or transmitted. Generally, a radio suitable for FHSS must allow for a very short blanking interval.
The Bluetooth protocol, for example, uses a time-division duplex (TDD) multiple-access scheme with 625 µs time slots (the time between hops), operating with 79 hop carriers in the 2.45 GHz ISM band. The time of occupancy (or dwell time) is a fraction of the 625 µs time slot and is defined as the period between hops during which a data packet gets transmitted (366 µs in Bluetooth, see http://mclean-linsky.net/joel/cv/1101Linsky74.pdf). The specification defines 234.5 µs of time between subsequent packets, including a ±10 µs reception window during which the radio remains tuned to the hop carrier. The remainder, 224.5 µs, is the blanking interval; the “hop” must be performed during that period.
Copyright Texas Instruments (http://www.ti.com/lit/an/swra077/swra077.pdf)
The Radio420X relies on serial peripheral interface (SPI) ports to control its behavior. The programming interface independently gives access to each SPI chip to facilitate programming and to avoid SPI access competition between the various parts of the designs. Therefore, there is no need to design a complex SPI port to simultaneously support different transfer lengths and polarities according to the target chip. The SPI bus interface is synchronized with the 100 MHz AXI clock.
Under normal operating conditions, the Radio420X is controlled by the MicroBlaze soft processor. The processor runs Nutaq’s Central Communication Engine (CCE) application and controls the SPI bus interfaces. For some purposes, it is preferable that the FPGA controls the Radio420X directly – for example, FPGA implementations of automatic gain control (AGC) algorithms or frequency-hopping spread spectrum (FHSS). Under normal operating conditions, the processor configures the default behavior of the Radio420X and releases the selected bus to the FPGA. Nutaq supplies, through its Board Support Package (BSP), Board Support Development Kit (BSDK), and Model-Based Design Kit (MBDK), a set of ports named “external control ports”. These ports give access to the SPI buses that control the Radio420X, the Lime Microsystem LMS6002D RFIC SPI bus being one of them. Here are the external control ports for controlling the Lime chip:
|iv16_limeSpiData_p||In||The 16-bit SPI data to send to the LMS6002D RFIC from the FPGA logic.[7:0]: Data [14:8]: Address : 0 = read, 1 = write|
|i_limeSpiStart_p||–||In||Starts an SPI transfer to the LMS6002D RFIC from the FPGA logic. The lime_data valid signal, a 1 means that lime_data will be sent to the chip.|
|o_limeSpiBusy_p||–||Out||Indicates that an SPI transfer is running on the LMS6002D RFIC bus. A 1 indicates that the chip is busy processing an SPI command|
|ov5_FpgaExtCtrl_p||[4:0]||Out||Indicates to the user logic which SPI core is FPGA control enabled. Each SPI core is represented with a bit (see Table 6 Offset 0x24 — SPI control in the LMS600D Programming and Calibration Guide).|
The SPI data to send to the Lime RF chip from FPGA logic is found in the LMS6002 Programming and Calibration Guide. A tutorial can be found on page 27 that describes the three main operations to be performed:
1. Set the FRANGE value.
2. Set the integer and fractional part of the divider.
3. Set the VCO CAP, charge pump current (Icp), and charge pump offset current (Ioff).
The values that need to been written to specific registers in order to complete the above three-step sequence to program the Tx and Rx PLLs are listed in a table on page 30 of the guide.
In a previous blog series, we saw how to drive the Radio420X core’s iv16_limeSpiData_p and i_limeSpiStart_p external control ports to switch the LMS6002D transmit and receive frequencies in the context of a cognitive radio application. An FPGA-based mean noise power calculator can detect if a channel is occupied during a silence period and, if required, switch frequencies before transmitting.
In another blog post we addressed the timing aspect of configuring the Tx and Rx frequency in a frequency hopping spread spectrum (FHSS) context. In this example, we considered hopping from an unknown sequence, with the possibility that every hop involves changing the frequency range using the values from the following table; the FRANGE value was overwritten on every hop.
|Frequency Range (GHz)||Value|
|0.2325 – 0.285625||100111|
|0.285625 – 0.336875||101111|
|0.336875 – 0.405||110111|
|0.405 – 0.465||111111|
|0.465 – 0.57125||100110|
|0.57125 – 0.67375||101110|
|0.67375 – 0.81||110110|
|0.81 – 0.93||111110|
|0.93 – 1.1425||100101|
|1.1425 – 1.3475||101101|
|1.3475 – 1.62||110101|
|1.62 – 1.86||111101|
|1.86 – 2.285||100100|
|2.285 – 2.695||101100|
|2.695 – 3.24||110100|
|3.24 – 3.72||111100|
Completing the three-step sequence means programming both the Tx and Rx PLLs (a total of 12 SPI register writes). On average, 270 clock cycles per SPI register write are needed. With a clock of 100 MHz, this means that:
1/100 MHz * 270 * 12 = 32.4 µs
In a case of “hopping” from a known sequence, such as with direct-sequence systems like Bluetooth, the hop sequence or spreading characteristics can be designed to avoid changing the frequency range (FRANGE) on each hop, which leads to a configuration time lower than 32.4 µs.
We’ll see in the next part of this blog series that Tx/Rx PLL configuration time is not the only factor to take into account when considering FHSS with the Radio420X. After the configuration commands are sent, the PLL settling time also has a determinant role in the blanking interval.